CY28347 Cypress Semiconductor, CY28347 Datasheet - Page 7

• Manufacturer Part Number: CY28347
• Description: Universal Single-chip Clock Solution
• Manufacturer: Cypress Semiconductor

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D
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t
Document #: 38-07352 Rev. *C
Table 8. Dial-A-Ratio™ AGP(0:2)
Byte 5: DDR Clock Register
Byte 6: Reserve Register
Byte 7: Dial-a-Frequency Control Register N
a
Bit
7
6
5
4
3
2
1
0
Bit
S
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
h
e
@Pup
e
0
1
1
1
1
1
1
1
t
@Pup
4
U
1
0
0
0
0
0
0
0
@Pup
.
0
0
0
0
0
0
0
0
DARAG (1:0)
c
29,30
31,32
35,36
37,38
41,42
43,44
Pin#
o
45
46
m
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
00
01
10
11
Reserved
N6, MSB
N5
N4
N3
N2
N1
N0, LSB
BUF_IN threshold voltage DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05V.
DDRT/C5
DDRT/C4
DDRT/C3
DDRT/C2
DDRT/C1
DDRT/C0
FBOUT
Name
Name
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
Reserved for device function test.
These bits are for programming the PLL’s internal N register. This
access allows the user to modify the CPU frequency at very high
resolution (accuracy). All other synchronous clocks (clocks that
are generated from the same PLL, such as PCI) remain at their
existing ratios relative to the CPU clock.
Description
Frequency Selection Default
CU/AGP Ratio
Description
2.5/1
Description
2/1
3/1
CY28347
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