CY28347 Cypress Semiconductor, CY28347 Datasheet - Page 17

• Manufacturer Part Number: CY28347
• Description: Universal Single-chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07352 Rev. *C
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The setup
PCI_STP#- Deassertion
The deassertion of the PCI_STP# signal will cause all PCI
clocks to resume running in a synchronous manner within one
PCI clock period after PCI_STP# transitions to a HIGH level.
Power Management Functions
All clocks can be individually enabled or stopped via the 2-wire
control interface. All clocks maintain valid HIGH period on
transitions from running to stop and on transitions from
stopped to running when the chip was not powered OFF.
PCI_STP#
PCI_STP#
PCI(1:6)
PCI(1:6)
PCI_F
PCI_F
Figure 12. PCI_STP# Deassertion Waveform
Figure 11. PCI_STP# Assertion Waveform
t
t
setup
setup
time for capturing PCI_STP# going LOW is 10 ns (t
PCI_F clock will not be affected by this pin.
Power Down Assertion (P4 Mode)
When PD# is sampled LOW by two consecutive rising edges
of CPUC clock then all clocks must be held LOW on their next
HIGH to LOW transition. CPUT clocks must be held with a
value of 2 x Iref,
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setup
). The