CY28347 Cypress Semiconductor, CY28347 Datasheet - Page 3

• Manufacturer Part Number: CY28347
• Description: Universal Single-chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07352 Rev. *C
Pin Description
Table 2. MODE Pin-Power Management Input Control
Table 3. Swing Select Functions Through Hardware
6
8
25
28
27
26
45
46
5
51
16
55
50
22
23
34,40
9
13
54
33,39
19
47
24
Pin
MULTSEL
(Latched Input)
MODE, Pin 6
MODE/AGP0
PCI_STP#
IREF
SDATA
SCLK
PD#
BUF_IN
FBOUT
VDDAGP
VDDC
VDDPCI
VDDR
VDDI
VDD48M
VDD
VDDD
VSSAGP
VSSPCI
VSSC
VSSD
VSS48M
VSSI
VSS
0
1
Invalid
0
Name
(continued)
VDDAGP I/O
VDDAGP
PWR
Board Target
Trace/Term Z
[2]
PD#
Reserved
50 Ohm
50 Ohm
I/O
PU
PU
I/O Serial Data Input. Conforms to the SMBus specification of a Slave
PU
O
I
I
I
I
I
Pin 26
Power-on Bidirectional Input/Output. At power-up, MODE is an input and
becomes AGP0 output after the power supply voltage crosses the input threshold
voltage. Must have 10K
If pin 6 is pulled down at power on reset, then this pin becomes PCI_STP#.
When PCI_STP# is asserted LOW, then all of the PCI signals, except the PCI_F,
stops at the next HIGH to LOW transition or stays LOW if it already is LOW.
Current reference programming input for CPU buffers. A precise resistor is
attached to this pin, which is connected to the internal current reference.
Receive/Transmit device. It is an input when receiving data. It is an open drain output
when acknowledging or transmitting data.
Serial Clock Input. Conforms to the SMBus specification.
When PD# is asserted LOW, the device enters power down mode. See power
management function.
2.5V CMOS type input to the DDR differential buffers.
This is the single-ended, SDRAM buffered output of the signal applied at
BUF_IN. It is in phase with the DDRT(0:5) signals.
3.3V power supply for AGP clocks.
3.3V power supply for CPU (T: C) clocks.
3.3V power supply for PCI clocks.
3.3V power supply for REF clock.
2.5V power supply for CPUCS_T/C clocks.
3.3V power supply for 48M.
3.3V Common power supply.
2.5V power supply for DDR clocks.
Ground for AGP clocks.
Ground for PCI clocks.
Ground for CPU (T:C) clocks.
Ground for DDR clocks.
Ground for 48M clock.
Ground for CPUCS_T/C clocks.
Common ground.
IREF = VDD/(3*Rr)
IREF = 5.00 mA
IREF = 2.32 mA
Reference R,
Rr = 221 1%,
Rr = 475 1%,
CPU_STP#
Reserved
resistor to V
Pin 18
Description
Output Current
IOH = 4* Iref
IOH = 6* Iref
SS
. See Table 2.
PCI_STP#
Reserved
Pin 8
1.0V@50
0.7V@50
VOH@Z
CY28347
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