LM3S328-IRN20-A0T Luminary Micro, Inc., LM3S328-IRN20-A0T Datasheet - Page 87

• Manufacturer Part Number: LM3S328-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

April 27, 2007
Reset
Reset
Type
Type
Bit/Field
31:17
15:12
Run-Mode, Sleep-Mode and Deep-Sleep-Mode Clock Gating Control 0 (RCGC0, SCGC0, and DCGC0)
Offset 0x100, 0x110, 0x120
11:8
16
RO
RO
31
15
0
0
Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100
Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110
Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will
generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that
all functional units are disabled. It is the responsibility of software to enable the ports necessary for
the application. Note that these registers may contain more bits than there are interfaces,
functions, or units to control. This is to assure reasonable code compatibility with other family and
future parts.
RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and
DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 82) specifies that the system uses sleep modes.
RO
RO
30
14
0
0
MAXADCSPD
reserved
reserved
reserved
Name
ADC
RO
RO
29
13
0
0
RO
RO
28
12
0
0
R/W
RO
27
11
0
0
Type
R/W
R/W
RO
RO
MAXADCSPD
R/W
RO
26
10
0
0
R/W
RO
Reset
25
0
9
0
0x0
Preliminary
0
0
0
reserved
R/W
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
This bit controls the clock gating for the ADC module. If
set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled.
Reserved bits return an indeterminate value, and should
never be changed.
This field sets the rate at which the ADC samples data.
You can set the sample rate by setting the MAXADCSPD bit
as follows (you cannot set the rate higher than the
maximum rate.):
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
Value
0x0
0x1
0x2
RO
RO
21
0
5
0
RO
RO
20
0
4
0
Sample Rate
125K samples/second
250K samples/second
500K samples/second
WDT
a
R/W
RO
19
0
3
0
LM3S328 Data Sheet
RO
RO
18
0
2
0
reserved
RO
RO
17
0
1
0
ADC
R/W
RO
16
0
0
0
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