LM3S328-IRN20-A0T Luminary Micro, Inc., LM3S328-IRN20-A0T Datasheet - Page 66

• Manufacturer Part Number: LM3S328-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
66
Reset
Reset
Type
Type
Bit/Field
31:17
15:12
Device Capabilities 1 (DC1)
Offset 0x010
11:8
16
7
6
5
4
3
2
1
RO
RO
31
15
0
0
Register 4: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features.
MINSYSDIV
RO
RO
30
14
0
1
MAXADCSPD
MINSYSDIV
reserved
reserved
TEMP
SWO
SWD
Name
WDT
ADC
MPU
PLL
RO
RO
29
13
0
1
a
a
a
a
RO
RO
28
12
0
1
a
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
MAXADCSPD
RO
RO
26
10
0
0
RO
RO
25
Reset
0
9
1
0x07
0x2
Preliminary
0
1
1
0
1
1
1
1
1
reserved
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this bit indicates the presence of the ADC module.
The reset value is hardware-dependent. A value of 0x7
specifies a 25-MHz clock with a PLL divider of 8. See the
RCC register (page 82) for how to change the system clock
divisor using the SYSDIV bit.
This field indicates the maximum rate at which the ADC
samples data. A value of 0x2 indicates 500K samples per
second.
This bit indicates whether the Memory Protection Unit
(MPU) in the Cortex-M3 is available. A 0 in this bit indicates
the MPU is not available; a 1 indicates the MPU is
available.
See the ARM® Cortex™-M3 Technical Reference Manual
for details on the MPU.
Reserved bits return an indeterminate value, and should
never be changed.
This bit specifies the presence of an internal temperature
sensor.
A 1 in this bit indicates the presence of an implemented
PLL in the device.
A 1 in this bit indicates a watchdog timer on the device.
A 1 in this bit indicates the presence of the ARM Serial Wire
Output (SWO) trace port capabilities.
A 1 in this bit indicates the presence of the ARM Serial Wire
Debug (SWD) capabilities.
MPU
RO
RO
23
0
7
1
reserved
RO
RO
22
0
6
0
TEMP
RO
RO
21
0
5
1
PLL
RO
RO
20
0
4
1
WDT
RO
RO
19
0
3
1
SWO
RO
RO
18
0
2
1
April 27, 2007
SWD
RO
RO
17
0
1
1
JTAG
ADC
RO
RO
16
1
0
1