LM3S328-IRN20-A0T Luminary Micro, Inc., LM3S328-IRN20-A0T Datasheet - Page 334

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LM3S328-IRN20-A0T

Manufacturer Part Number
LM3S328-IRN20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
Inter-Integrated Circuit (I2C) Interface
334
Write-Only Control Register
Bit/Field
31:1
1
0
0
reserved
TREQ
RREQ
Name
DA
Type
WO
RO
RO
RO
Reset
Preliminary
0
0
0
0
Description
This bit specifies the state of the I
outstanding transmit requests. If set, the I
addressed as a slave transmitter and uses clock
stretching to delay the master until data has been written
to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
Receive Request
This bit specifies the status of the I
to outstanding receive requests. If set, the I
outstanding receive data from the I
clock stretching to delay the master until the data has
been read from the I2CSDR register. Otherwise, no
receive data is outstanding.
Reserved bits return an indeterminate value, and should
never be changed.
Device Active
1=Enables the I
0=Disables the I
2
2
C slave operation.
C slave operation.
2
C slave with regards to
2
2
C slave with regards
C master and uses
2
C unit has been
2
C unit has
April 27, 2007

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