LM3S328-IRN20-A0T Luminary Micro, Inc., LM3S328-IRN20-A0T Datasheet - Page 318

• Manufacturer Part Number: LM3S328-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Inter-Integrated Circuit (I2C) Interface
14.4
Table 14-2. I
14.5
318
Offset
0x00C
0x01C
0x00C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x000
0x004
0x008
0x010
0x014
0x018
Name
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIMR
I2CSRIS
I2CSMIS
I2CSICR
7.
8.
Register Map
Table 14-2 lists the I
master and slave:
Register Descriptions (I
The remainder of this section lists and describes the I
address offset. See also “Register Descriptions (I2C Slave)” on page 332.
2
C Register Map
Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x00000007 (STOP, START, RUN).
Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
I
I
2
2
C Master: 0x40020000
C Slave: 0x40020800
0x00000000
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
2
C registers. All addresses given are relative to the I
Reset
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
WO
RO
RO
RO
RO
RO
Preliminary
2
C Master)
Description
Master slave address
Master control/status
Master data
Master timer period
Master interrupt mask
Master raw interrupt status
Master masked interrupt status
Master interrupt clear
Master configuration
Slave address
Slave control/status
Slave data
Slave interrupt mask
Slave raw interrupt status
Slave masked interrupt status
Slave interrupt clear
2
C master registers, in numerical order by
2
C base addresses for the
April 27, 2007
See
page
319
320
325
326
327
328
328
329
330
332
333
335
336
337
338
339