LM3S317-IQN20-A0T Luminary Micro, Inc., LM3S317-IQN20-A0T Datasheet - Page 68

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LM3S317-IQN20-A0T

Manufacturer Part Number
LM3S317-IQN20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
System Control
a. These bits mask the Run-Mode Clock Gating Control 0 (RCGC0) register (see page 113), Sleep-Mode Clock Gating Control 0
68
Bit/Field
(SCGC0) register (see page 113), and Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 113). Bits that are
not noted are passed as 0. ADCSP is clipped to the maximum value specified in DC1.
2
1
0
JTAG
SWO
SWD
Name
a
a
a
Type
RO
RO
RO
Reset
Preliminary
1
1
1
Description
A 1 in this bit indicates the presence of the ARM Serial Wire
Output (SWO) trace port capabilities.
A 1 in this bit indicates the presence of the ARM Serial Wire
Debug (SWD) capabilities.
A 1 in this bit indicates the presence of a JTAG port.
May 4, 2007

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