LM3S317-IQN20-A0T Luminary Micro, Inc., LM3S317-IQN20-A0T Datasheet - Page 329

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LM3S317-IQN20-A0T

Manufacturer Part Number
LM3S317-IQN20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
May 4, 2007
Bit/Field
31:
1
0
Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the
fault input and debug events are considered fault conditions. On a fault condition, each PWM
signal can either be passed through unmodified or driven Low. For outputs that are configured for
pass-through, the debug event handling on the corresponding PWM generator also determines if
the PWM signal continues to be generated.
Fault condition control happens before the output inverter, so PWM signals driven Low on fault are
inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault
condition).
reserved
Fault1
Fault0
Name
Type
R/W
R/W
RO
Reset
0
0
0
Preliminary
Description
never be changed.
When set, the PWM1 output signal is driven Low on a fault
condition.
When set, the PWM0 output signal is driven Low on a fault
condition.
Reserved bits return an indeterminate value, and should
LM3S317 Data Sheet
329

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