LM3S317-IQN20-A0T Luminary Micro, Inc., LM3S317-IQN20-A0T Datasheet - Page 327
LM3S317-IQN20-A0T
Manufacturer Part Number
LM3S317-IQN20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S317-IQN20-A0T.pdf
(379 pages)
- Current page: 327 of 379
- Download datasheet (3Mb)
May 4, 2007
Bit/Field
31:
1
0
Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated PWM signals are output to device pins.
By disabling a PWM output, the generation process can continue (for example when the time
bases are synchronized) without driving PWM signals to the pins. When bits in this register are
set, the corresponding PWM signal is passed through to the output stage, which is controlled by
the PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value
which is also passed to the output stage.
PWM1En
PWM0En
reserved
Name
Type
R/W
R/W
RO
Reset
0
0
0
Preliminary
Description
Reserved bits return an indeterminate value, and should
never be changed.
When set, allows the generated PWM1 signal to be passed
to the device pin.
When set, allows the generated PWM0 signal to be passed
to the device pin.
LM3S317 Data Sheet
327
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