LM3S317-IQN20-A0T Luminary Micro, Inc., LM3S317-IQN20-A0T Datasheet - Page 346
LM3S317-IQN20-A0T
Manufacturer Part Number
LM3S317-IQN20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S317-IQN20-A0T.pdf
(379 pages)
- Current page: 346 of 379
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Pulse Width Modulator (PWM)
346
Reset
Reset
Type
Type
Bit/Field
31:12
PWMn Dead-Band Rising-Edge Delay (PWMnDBRISE)
11:0
RO
RO
31
15
0
0
Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the
PWM0A signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay.
RO
RO
30
14
0
0
reserved
RiseDelay
reserved
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
RO
RO
27
11
0
0
R/W
RO
26
10
0
0
Reset
R/W
RO
25
0
9
0
0
0
Preliminary
R/W
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
The number of clock ticks to delay the rising edge.
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
RiseDelay
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
May 4, 2007
0
1
0
R/W
RO
16
0
0
0
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