AD6641 Analog Devices, AD6641 Datasheet - Page 7

• Manufacturer Part Number: AD6641
• Description: 250 MHz Bandwidth DPD Observation Receiver
• Manufacturer: Analog Devices

Parameter
LOGIC OUTPUTS
1
2
SWITCHING SPECIFICATIONS
AVDD = 1.9 V, DRVDD = 1.9 V, T
Table 4.
Parameter
OUTPUT DATA RATE
PULSE WIDTH/PERIOD (CLK±)
PULSE WIDTH/PERIOD (PCLK±, DDR LVDS MODE)
SERIAL PORT OUTPUT TIMING
SERIAL PORT INPUT TIMING
FILL± INPUT TIMING
APERTURE DELAY (t
APERTURE UNCERTAINTY (JITTER, t
1
2
See the
completed.
5 pF loading.
See the
completed.
5 pF loading.
DDR LVDS Mode (PCLK±, PD[5:0]±, PDOR±)
Parallel CMOS Mode (PCLK±, PD[11:0])
Low Level Output Voltage
Output Coding
Maximum Output Data Rate (Decimate by 8 at 500 MSPS Sample Rate, Parallel CMOS
Maximum Output Data Rate (Decimate by 8 at 500 MSPS Sample Rate, SPORT Mode)
CLK± Pulse Width High (t
CLK± Pulse Width Low (t
Rise Time (t
Fall Time (t
PCLK± Pulse Width High (t
PCLK± Period (t
Propagation Delay (t
Rise Time (t
Fall Time (t
Data to PCLK Skew (t
SP_SDFS Propagation Delay (t
SP_SDO Propagation Delay (t
SP_SDFS Setup Time (t
SP_SDFS Hold Time (t
FILL± Setup Time (t
FILL± Hold Time (t
Logic Compliance
V
V
Logic Compliance
High Level Output Voltage
or DDR LVDS Mode Interface)
OD
OS
AN-835
AN-835
Differential Output Voltage
Output Offset Voltage
1
1
F
F
R
) (20% to 80%)
R
) (20% to 80%)
Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
) (20% to 80%)
) (20% to 80%)
PCLK
A
)
Hfill
)
Sfill
CPD
)
SKEW
HSF
)
SSF
, CLK± to PCLK±)
)
CL
)
)
CH
)
PCLK_CH
)
2
DSDO
DSDFS
)
J
MIN
)
)
)
= −40°C, T
MAX
= +85°C, f
Rev. 0 | Page 7 of 28
Temp
Full
Full
Full
Full
Full
Full
IN
= −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Min
DRVDD − 0.05
247
1.125
Twos complement, Gray code, or offset binary (default)
Temp
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
AD6641-500
Typ
CMOS
LVDS
Min
62.5
62.5
Max
454
1.375
DRGND + 0.05
AD6641-500
Typ
1
1
0.2
0.2
8
16
±0.1
0.2
0.2
0.2
3
3
2
2
0.5
0.7
0.85
80
Max
AD6641
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fs rms
Unit
mV
V
V
V
MHz