AD6641 Analog Devices, AD6641 Datasheet - Page 27

• Manufacturer Part Number: AD6641
• Description: 250 MHz Bandwidth DPD Observation Receiver
• Manufacturer: Analog Devices

ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD6641 is a differential buffer. For
best dynamic performance, match the source impedances
driving VIN+ and VIN− such that common-mode settling
errors are symmetrical. The analog input is optimized to provide
superior wideband performance and requires that the analog
inputs be driven differentially. SNR and SINAD performance
degrades significantly if the analog input is driven with a single-
ended signal.
A wideband transformer, such as Mini-Circuits® ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip reference to a nominal 1.7 V.
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.5 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of an SPI control.
VREF
The AD6641 VREF pin (Pin 31) allows the user to monitor the
on-board voltage reference or provide an external reference
(requires configuration through the SPI). The three optional
settings are internal V
export V
to this pin. VREF is internally compensated and additional
loading may impact performance.
CONFIGURATION USING THE SPI
Three pins define the SPI of the AD6641: SCLK, SDIO, and CSB
(see Table 11). SCLK (a serial clock) is used to synchronize the
read and write data presented from and to the AD6641. SDIO
(serial data input/output) is a bidirectional pin that allows data
to be sent to and read from the internal memory map registers.
CSB (chip select) is an active low control that enables or disables
the read and write cycles.
SCLK
SDIO
CSB
REF
DON’T
CARE
DON’T
CARE
, and import V
t
S
R/W
REF
t
(pin is connected to 20 kΩ to ground),
DS
REF
W1
. Do not attach a bypass capacitor
W0
t
DH
A12
t
HIGH
A11
Figure 43. Serial Port Interface Timing Diagram
t
LOW
A10
A9
t
CLK
Rev. 0 | Page 27 of 28
A8
A7
Table 11. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
The falling edge of the CSB pin, in conjunction with the rising
edge of the SCLK pin, determines the start of the framing. An
example of the serial timing can be found in Figure 43 (for
symbol definitions, see Table 5).
CSB can be held low indefinitely, which permanently enables
the device; this is called streaming. CSB can stall high between
bytes to allow additional external timing. When CSB is tied
high, SPI functions are placed in high impedance mode.
During an instruction phase, a 16-bit instruction is transmitted.
The first bit of the first byte in a serial data transfer frame indicates
whether a read command or a write command is issued. Data
follows the instruction phase, and its length is determined by
the W0 and W1 bits. All data is composed of 8-bit words.
The instruction phase determines whether the serial frame is a
read or write operation, allowing the serial port to be used both
to program the chip and to read the contents of the on-chip
memory. If the instruction is a read operation, the serial data
input/output (SDIO) pin changes direction from an input to an
output at the appropriate point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default mode on power-up and can be changed via
the SPI port configuration register. For more information about
this and other features, see the
Interfacing to High Speed ADCs via SPI.
D5
Function
Serial clock. Serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
Serial data input/output. Bidirectional pin that serves
as an input or an output, depending on the instruction
being sent and the relative position in the timing frame.
Chip select (active low). This control gates the read and
write cycles.
D4
D3
D2
AN-877
D1
Application Note,
D0
t
H
DON’T CARE
DON’T CARE
AD6641