AD6641 Analog Devices, AD6641 Datasheet - Page 23

• Manufacturer Part Number: AD6641
• Description: 250 MHz Bandwidth DPD Observation Receiver
• Manufacturer: Analog Devices

THEORY OF OPERATION
The on-chip FIFO allows small snapshots of time to be captured
via the ADC and read back at a lower rate. This reduces the
constraints of signal processing by transferring the captured
data at an arbitrary time and at a much lower sample rate.
FIFO OPERATION
The capture of the data can be signaled through writes to the
SPI port by pulsing the FILL± pins. The transaction diagram
shown in Figure 36 illustrates the loading of the FIFO.
At Event 1, the FIFO is instructed to fill either by asserting the
FILL± pins or via a write to the SPI bits. FILL± pin operation
can be delayed by a programmable fill hold-off counter so that
the FIFO data can be surrounding a fill event. The FIFO then
loads itself with data. The number of samples of data is
determined by the SPI fill count register (0x104). This is an 8-
bit register with values from 0 to 255. The number of samples
placed in the FIFO is determined by the following equation:
After the FIFO has begun filling at Event 2, the AD6641 asserts
a full flag to indicate that the FIFO has finished capturing data
and enters a wait state in which the device waits to receive the
dump instruction from the DUMP pin or the SPI.
After the data has been shifted (Event 4), the FIFO goes into the
idle state and waits for another fill command. During the idle
state, the ADC can optionally be placed into standby mode to
save power. If the ADC powers down in the idle state, initiating
a fill operation (Event 1) powers up the ADC. In this mode, the
ADC waits for settle count cycles (0x105, 0x106) before capturing
the data. Settle count is programmable from the SPI port and
Number of Samples = (FILL_CNT + 1) × 64
EVENTS
STATE
IDLE STATE
FILL+, FILL–
DUMP
CLK+
CLK–
CLK+
CLK–
1
FILLING FIFO WITH DATA
Figure 36. On-Chip FIFO Transaction Timing Assuming Serial Port
2
WAIT FOR DUMP (OPTIONAL)
Figure 38. FIFO DUMP Timing
Figure 37. FIFO Fill Timing
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allows the analog circuitry to stabilize before taking data. An
intelligent trade-off between speed of acquisition and accuracy
can be made by using this register.
The data can be read back through any of the three output inter-
faces at a low data rate, which further saves power. If the SPI or
SPORT is used to read back the data, the interface can require
as few as three pins. A full flag and an empty flag are provided
to signal the state of the FIFO. The FIFO status register (0x10A)
in the SPI also allows this to be monitored via software.
Single Capture Mode
The FIFO can be placed into single capture mode by writing the
FIFO fill mode bits in the fill control register (0x101[3:2]) to 00.
In the single capture mode, the user initiates a capture either by
driving the FILL± pins high or by initiating a fill command
through the SPI port by writing the standby after fill bit
(0x101[0]). This powers up the ADC (if needed) after a
programmable amount of time as determined by the SPI settle
count registers (0x105, 0x106). If Bit 0 of the 0x101 register in
the SPI is set, the ADC returns to standby mode after the
capture is complete.
Fill Pin Timing
A fill of the FIFO can be initiated by asserting the differential
FILL± pins. When a pulse is detected on the FILL± pins, the
FIFO is filled.
Dump Pin Timing
A readback of the FIFO can be initiated by asserting the DUMP
pin. When a logic high is detected on the DUMP pin, the FIFO
data is available through the chosen interface.
3
START SP_SCLK AND SP_SDFS SHIFT DATA
4
IDLE STATE
AD6641