AD6641 Analog Devices, AD6641 Datasheet - Page 26

• Manufacturer Part Number: AD6641
• Description: 250 MHz Bandwidth DPD Observation Receiver
• Manufacturer: Analog Devices

FIFO OUTPUT INTERFACES
The FIFO data is available through one of three interfaces. The
data can be output on the serial data port (SPORT), the SPI
port, or a 12-bit CMOS interface. The data port chosen must be
selected from the SPI port before the data is read from the FIFO.
Only one interface can be chosen at a time. The SPORT and SPI
interfaces are powered via the SPI_VDDIO pin and can support
either 1.9 V or 3.3 V logic levels.
SPORT Interface
The SPORT consists of a clock (SP_SCLK) and frame sync
(SP_SDFS) signal. The SP_SCLK and SP_SDFS signals are
output from the AD6641 when the SPORT is configured as
a bus master and are input to the device when it is configured
as a slave port.
Serial Data Frame (Serial Bus Master)
The serial data transfer is initiated with SP_SDFS. In master
mode, the internal serial controller initiates SP_SDFS after the
dump input goes high requesting the data. SP_SDFS is valid for
one complete clock cycle prior to the data shift. On the next
clock cycle, the AD6641 begins shifting out the data stream.
CMOS Output Interface
The data stored in the FIFO can also be accessed via a 12-bit
parallel CMOS interface. The maximum output throughput
supported by the AD6641 is in the 12-bit CMOS mode and is
internally limited to 1/8
Therefore, the output maximum output data rate is 62.5 MHz
AD6641
SP_SCLK
SP_SDFS
PD[5:0]±
SP_SDO
PCLK+
PCLK–
th
of the maximum input sample rate.
X
0
D0[5:0]
D0 SAMPLE
LSB/MSB
Figure 42. DDR LVDS Output MSB/LSB Interleaving with Decimate by 8
4
D0[11:6]
D1
Figure 41. Data Output in Serial Bus Master Mode
8
D8[5:0]
D8 SAMPLE
LSB/MSB
12
Rev. 0 | Page 26 of 28
D8[11:6]
16
D16[5:0]
at a 500 MSPS input sample rate. See Figure 3 for the parallel
CMOS mode output interface timing diagram.
LVDS Output Interface
The AD6641 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to a
low power, reduced signal option similar to the IEEE 1596.3
standard using the SPI. This LVDS standard can further reduce
the overall power dissipation of the device, which reduces the
power by ~39 mW. The LVDS driver current is derived on chip
and sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal ±350 mV differential
or 700 mV p-p swing at the receiver.
The AD6641 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths.
The data on the LVDS output port is interleaved in a MSB/LSB
format. PCLK± is generated by dividing the ADC sample clock
by the programmed decimation rate (8 to 32, even divides). The
maximum rate of PCLK± is limited to 62.5 MHz.
20
D16[11:6]
D2
24
D24[5:0]
28
D24[11:6]
D3