AD6641 Analog Devices, AD6641 Datasheet - Page 6

• Manufacturer Part Number: AD6641
• Description: 250 MHz Bandwidth DPD Observation Receiver
• Manufacturer: Analog Devices

DIGITAL SPECIFICATIONS
AVDD = 1.9 V, DRVDD = 1.9 V, T
Table 3.
Parameter
CLOCK INPUTS (CLK±)
LOGIC INPUTS (SPI, SPORT)
LOGIC INPUTS (DUMP, CSB)
LOGIC INPUTS (FILL±)
LOGIC OUTPUTS
LOGIC OUTPUTS
AD6641
Logic Compliance
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
High Level Input Current (I
Low Level Input Current (I
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current (SDIO)
Logic 0 Input Current (SDIO)
Logic 1 Input Current (SCLK)
Logic 0 Input Current (SCLK)
Input Capacitance
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current
Logic 0 Input Current
Input Capacitance
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
High Level Input Current (I
Low Level Input Current (I
Input Resistance (Differential)
Input Capacitance
Logic Compliance
High Level Output Voltage
Low Level Output Voltage
Logic Compliance
High Level Output Voltage
Low Level Output Voltage
High Level Input (V
Low Level Input (V
High Level Input (V
Low Level Input (V
1
2
2
(SPI, SPORT)
(FULL, EMPTY)
IL
IL
IH
IH
)
)
)
)
IL
IL
IH
IH
)
)
)
)
MIN
= −40°C, T
MAX
= +85°C, f
Rev. 0 | Page 6 of 28
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
IN
= −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Min
0.2
−1.8
−10
−10
8
0.8 × SPI_VDDIO
0.8 × DRVDD
0.2
−1.8
−10
−10
8
DRVDD − 0.05
SPI_VDDIO − 0.05
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
AD6641-500
Typ
0.9
10
4
0
−60
50
0
4
0
−60
4
0.9
10
4
CMOS
CMOS
CMOS
CMOS
Max
1.8
−0.2
+10
+10
12
0.2 × SPI_VDDIO
0.2 × DRVDD
1.8
−0.2
+10
+10
12
DRGND + 0.05
DRGND + 0.05
Unit
V
V p-p
V p-p
μA
μA
kΩ
pF
V
V
μA
μA
μA
μA
pF
V
V
μA
μA
pF
V
V p-p
V p-p
μA
μA
kΩ
pF
V
V
V
V