AD6641 Analog Devices, AD6641 Datasheet - Page 22

• Manufacturer Part Number: AD6641
• Description: 250 MHz Bandwidth DPD Observation Receiver
• Manufacturer: Analog Devices

Addr.
(Hex)
0x105
0x106
0x107
0x10A
0x10B
0x10C
0x10F
0x110
0x111
0x112
0x13A
1
AD6641
X = don’t care.
Settle Count0
Settle Count1
Dump control
FIFO status
FIFO Dump Data0
FIFO Dump Data1
Read Offset Data0
Read Offset Data1
PPORT control
SPORT control
FIFO test BIST
Parameter Name
Bit 7
(MSB)
[7:6] = reserved
[7:5] = reserved
[7:5] = reserved
[7:5] = reserved
Bit 6
[7:4] = reserved
[7:3] = reserved
[7:3] = reserved
Bit 5
Rev. 0 | Page 22 of 28
Bit 4
0011 = checkerboard (12'hAAA, 12'h555,
0010 = checkerboard (12'h555, 12'hAAA,
[7:0] = LSBs
[7:0] = LSBs
Sets the BIST mode for the FIFO:
[7:0]
[7:0]
0001 = decrementing ramp
0000 = incrementing ramp
0110 = 12'hFFF (−1 LSB)
0101 = 12'h001 (+1 LSB)
Bit 3
00100 = divide by 8 (default)
00100 = divide by 8 (default)
Divide ratio = 2 × (bit word):
0111 = reserved
1xxx = reserved
Divide ratio= 2 × (bit word):
0100 = PN data
12'hAAA, … )
[5:0] = MSBs
12'h555, … )
01111 = divide by 30
01111 = divide by 30
1xxxx = divide by 32
1xxxx = divide by 32
0 =
slave
1 =
master
Over-
range
Bit 2
…
…
[3:0] = MSBs
Bit 1
Empty
Readback mode:
11 = reserved
01 = parallel
10 = SPORT
00 = off
Bit 0
(LSB)
Full
FIFO
BIST
enable
0
0
0
0
0
0x04
0x04
Default
Value
(Hex)
0
0
0
0
Default
Notes/
Comments
LSBs settling
time given to
ADC before
initiating fill.
MSBs settling
time given to
ADC before
initiating fill.
Customer
drives
SP_SCLK,
SP_SDFS in
slave mode.
LSBs readback
data.
MSBs upper
four bits
readback
data.
LSBs offset to
RAM, allowing
subsegments
of data cap-
ture to be
read.
MSB’s offset.
CMOS parallel
port divide
rate.
Serial port
divide rate.