MT90871 Zarlink Semiconductor, MT90871 Datasheet - Page 63

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MT90871

Manufacturer Part Number
MT90871
Description
Flexible 8K Digital Switch (F8KDX)
Manufacturer
Zarlink Semiconductor
Datasheet

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Data Sheet
Note 1:
Note: There must be a minimum of 30ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e. a minimum of 30ns must separate the de-assertion of DTA_b (to high) and the assertion
of CS_b and/or DS_b (to initiate the next access).
Non-Multiplexed Microprocessor Port Timing
10
12
11
1
2
3
4
5
6
7
8
9
A0-A14
D0-D15
READ
D0-D15
WRITE
High impedance is measured by pulling to mid-rail with R
to discharge C
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
Data setup on write
Data hold on write
Acknowledgment Delay:
Acknowledgment Hold Time
DS
CS
R/W
DTA
Reading/Writing Registers
Reading/Writing Memory
Characteristics
L
.
Figure 29 - Motorola Non-Multiplexed Bus Timing
Zarlink Semiconductor Inc.
t
t
t
t
t
Sym
t
t
t
t
t
t
t
t
t
ADS
CSS
RWS
RWH
WDS
DHW
CSH
ADH
DDR
DHR
t
CSS
ADS
AKD
AKH
RWS
Min
t
L
14
WDS
0
8
8
0
8
8
8
8
= 1K/1K potential divider, with timing corrected to cancel time taken
Typ
VALID ADDRESS
t
AKD
t
Max
DDR
VALID WRITE DATA
30
85
70
12
VALID READ DATA
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
C
L
L
=60pF, R
=60pF, R
t
t
CSH
Test Conditions
DHW
t
DHR
t
t
RWH
ADH
C
C
C
t
L
L
L
AKH
=60pF
=60pF
=60pF
L
L
=1K, Note 1
=1K, Note 1
V
V
V
V
V
V
V
TT
TT
TT
TT
TT
TT
TT
63

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