MT90871 Zarlink Semiconductor, MT90871 Datasheet - Page 37

• Manufacturer Part Number: MT90871
• Description: Flexible 8K Digital Switch (F8KDX)
• Manufacturer: Zarlink Semiconductor

Data Sheet
When BPE is HIGH, no other bits of the BPR register must be changed for at least a single frame period, except
to abort the programming operation. The programming operation may be aborted by setting either BPE to LOW,
or the Control Register bit, MBP, to LOW.
The BPR register is configured as follows.
13.3
Address 0002h.
The BER control register controls Backplane and Local port BER testing. It independently enables and
disables transmission and reception. It is configured as follows:
15-12
15-7
6-4
3-1
Bit
Bit
11
10
0
9
BBPD(2:0)
LBPD(2:0)
Reserved
LOCKB
PRSTB
CBERB
Unused
Name
BPE
Name
Bit Error Rate Test Control Register (BERCR)
Table 15- Bit Error Rate Test Control Register (BERCR) Bits
Reset
RESET
0
0
0
0
0
0
0
0
Table 14- Block Programming Register Bits
Set LOW.
Backplane Block Programming Data.
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated. When the
MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the
contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM.
Bits 12-0 of the BCM are set LOW
Local block Programming Data.
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated. When the MBP bit in
the Control Register is set HIGH and the BPE is set HIGH, the contents of Bits
LBPD2-0 are loaded into Bits 15-13, respectively, of the LCM.
Bits 12-0 of the LCM are set LOW
Block Programming Enable.
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125us, upon completion of programming.
Set LOW to abort the programming operation.
Reserved.
Backplane Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXB.
PBER Reset for Backplane.
A LOW to HIGH transition initializes the Backplane BER generator to the
seed value.
Clear Bit Error Rate Register for Backplane.
A LOW to HIGH transition in this bit resets the Backplane internal bit error
counter and the Backplane bit error (BBERR) register to zero.
Zarlink Semiconductor Inc.
Description
Description
37
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