MT90871 Zarlink Semiconductor, MT90871 Datasheet - Page 36

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MT90871

Manufacturer Part Number
MT90871
Description
Flexible 8K Digital Switch (F8KDX)
Manufacturer
Zarlink Semiconductor
Datasheet

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13.2
Address 0001h.
The block programming register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR register must
be defined in the same write operation.
The BPE bit is set HIGH, to commence the block programming operation. Programming is completed in one frame
period and may be be instigated at any time within a frame.The BPE bit returns to LOW to indicate the block
programming function has completed.
36
(g)
(e)
(f)
(h)
Block Programming Register (BPR)
Pulse Width = 244ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 0
Pulse Width = 122ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 0
Pulse Width = 122ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
Pulse Width = 244ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
FP8i_b
FP8i_b
FP8i_b
FP8i_b
C8i_b
C8i_b
C8i_b
C8i_b
Figure 18 - Frame Boundary Conditions, GCI - BUS Operation
Zarlink Semiconductor Inc.
Frame Boundary
Data Sheet

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