MT90871 Zarlink Semiconductor, MT90871 Datasheet - Page 51

• Manufacturer Part Number: MT90871
• Description: Flexible 8K Digital Switch (F8KDX)
• Manufacturer: Zarlink Semiconductor

Data Sheet
13.14
Address 3FFFh
The revision control register stores the binary value of the silicon revision number. This register is read only.
The RCR register is configured as follows:
15-4
Bit
3-0
Bit
10
9
8
7
6
5
4
3
2
1
0
BISTCDB
BISTPDB
BISTSCB
BISTCCB
BISTPCB
BISTSDL
BISTCDL
BISTPDL
BISTSCL
BISTCCL
BISTPCL
Name
Reserved
RC(3:0)
Revision Control Register
Name
Reset
Table 46- Memory BIST Register (MBISTR) Bits (continued)
0
0
0
0
0
0
0
0
0
0
0
Table 47- Revision Control Register (RCR) Bits
defined by silicon
Backplane Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
Backplane Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Local Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
Local Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
Local Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Backplane Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
Backplane Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
Backplane Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Local Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
Local Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
Local Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Reset Value
0
Zarlink Semiconductor Inc.
Reserved.
Revision Control Bits.
Description
Description
51