MT90871 Zarlink Semiconductor, MT90871 Datasheet - Page 26

• Manufacturer Part Number: MT90871
• Description: Flexible 8K Digital Switch (F8KDX)
• Manufacturer: Zarlink Semiconductor

The Control Register bits MS2, MS1, and MS0 must be set to 000, respectively, to select the Local Connection
Memory for the Write and Read operations via the microprocessor port. See Section 7.0 "Microprocessor
Port", and Section 13.1 "Control Register (CR)" for details on microprocessor port access.
6.2
The Backplane Connection Memory (BCM) is 16-bit wide with 4,096 memory locations to support the
Backplane output port. The most significant bit of each word, bit [15], selects the source stream from either the
Backplane or the Local port and determines the Local-to-Backplane or Backplane-to-Backplane data routing.
Bits [14:13] select the control modes of the Backplane output streams, namely the per-channel Message Mode
and the per-channel high impedance output control mode. In Connection Mode (Bit14 = LOW), Bits [12:0]
select the source stream and channel number as detailed in Table 4. In Message Mode (Bit14 = HIGH), Bits
[12:8] are unused and Bits [7:0] contain the message byte to be transmitted.
The Control Register bits MS2, MS1, and MS0 must be set to 001, respectively, to select the Backplane
Connection Memory for the Write and Read operations via the microprocessor port. See Section 7.0, and
Section 13.1.
6.3
This feature allows fast simultaneous initialization of the Local and Backplane Connection Memories after
power up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 13 and Table 14 for details of the
Control Register and Block Programming Register values, respectively.
6.3.1
•
•
The Backplane Block Programming data bits, BBPD2-0, of the Block Programming Register, will be loaded into
Bit 15, Bit 14 and Bit 13, respectively, of the Backplane Connection Memory. The remaining bit positions are
loaded with zeros as shown in Table 6.
26
LBPD2
Set the MBP bit in the Control Register from LOW to HIGH.
Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD2-0, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively, of
the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 5.
15
Backplane Connection Memory
Connection Memory Block Programming
Memory Block Programming Procedure
Source Stream Bit Rate
LBPD1
Table 4- Local and Backplane Connection Memory Configuration
14
Table 5- Local Connection Memory in Block Programming Mode
16Mb/s
2Mb/s
4Mb/s
8Mb/s
LBPD0
13
12
0
11
0
Zarlink Semiconductor Inc.
Source Stream No.
10
legal values 0 - 15
legal values 0 - 15
legal values 0 - 15
legal values 0 - 15
0
9
0
[12:8]
[12:8]
[12:8]
[12:8]
8
0
7
0
6
0
5
0
Source Channel No.
legal values 0 - 127
legal values 0 - 255
legal values 0 - 31
legal values 0 - 63
4
0
[7:0]
[7:0]
[7:0]
[7:0]
3
0
2
0
Data Sheet
1
0
0
0