MT90871 Zarlink Semiconductor, MT90871 Datasheet - Page 48

• Manufacturer Part Number: MT90871
• Description: Flexible 8K Digital Switch (F8KDX)
• Manufacturer: Zarlink Semiconductor

13.10.4
Address 00CBh
Backplane BER Start Receive Register defines the Input Stream and the Start Channel in which the BER sequence
shall be received. The BBSRR register is configured as follows:
13.10.5
Address 00CCh
Backplane BER Count Register contains the number of counted errors. This register is read only. The BBCR
register is configured as follows:
13.11
13.11.1
Address 00CDh to 00DCh.
Sixteen Local Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or
16 Mb/s. The LIBRR registers are configured as follows:
48
(for n=0 to 15)
15-13
15-0
12-9
Bit
8-0
Bit
LIBRn
15-2
1-0
BBRSA(3:0)
BBRCA(8:0)
BBC(15:0)
Reserved
Name
Local Bit Rate Registers
Backplane BER Start Receive Register (BBSRR)
Backplane BER Count Register (BBCR)
Local Input Bit Rate Registers (LIBRR0-15)
Name
Reserved
LIBR(1:0)
Name
Table 36- Backplane BER Start Receive Register (BBSRR) Bits
Table 37- Backplane BER Count Register (BBCR) Bits
Reset
Table 38- Local Input Bit Rate Register (LIBRRn) Bits
Reset
0
0
0
0
Reset
Reserved.
Backplane BER Receive Stream Address Bits
The binary value of these bits defines the Backplane input stream that
receives the BER data.
Backplane BER Receive Channel Address Bits
The binary value of these bits define the Backplane input Start Channel in
which the BER data will be received.
Backplane Bit Error Rate Count
The binary value of these bits define the Backplane Bit Error count.
0
0
Reserved
Local Input Bit Rate
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