MT90871 Zarlink Semiconductor, MT90871 Datasheet
MT90871
Available stocks
Related parts for MT90871
MT90871 Summary of contents
Page 1
... Connection Memory (4,096 locations) (4,096 locations) Local Data Memories (4,096 channels) Microprocessor Interface and Internal Registers DD_PLL DS CS R/W A14-A0 DTA D15-D0 Figure 1 - MT90871 Functional Block Diagram Zarlink Semiconductor Inc. Data Sheet Ordering Information MT90871AV 196 Ball LBGA -40C to +85C ODE RESET ...
Page 2
... Digital Loop Carriers Device Overview The MT90871 has two data ports, the Backplane and the Local port. The Backplane port has 16 input and 16 output streams operated at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, in any combination and the Local port has 16 input and 16 output streams operated at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, in any combination ...
Page 3
... The microprocessor may monitor channel data in the Backplane and Local data memories. The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port. The MT90871 is manufactured in a 15mm x 15mm body, 1.0mm ball-pitch, 196-LBGA to JEDEC standard MS-034 BAL-2 Iss. A. ...
Page 4
... Backplane output streams on a per channel basis. BCSTo0 is the output enable for BSTo[ 10, 12, 14], BCSTo1 is the output enable for BSTo[ 11, 13, 15]. Refer to descriptions of the BORS and ODE pins for control of the output High or High-Impedance state. Zarlink Semiconductor Inc. Data Sheet ...
Page 5
... LORS and BORS external control pins, respectively. It clears the device registers and internal counters. This pin must stay low for more than 2 cycles of input clock C8i for the reset to be invoked. Zarlink Semiconductor Inc. 5 ...
Page 6
... Local output streams on a per channel basis. LCSTo0 is the output enable for LSTo[ 10, 12, 14], LCSTo1 is the output enable for LSTo[ 11, 13, 15]. Refer to descriptions of the LORS and ODE pins for control of the output High or High-Impedance state. Zarlink Semiconductor Inc. Data Sheet ...
Page 7
... Backplane stream outputs may be set active or high impedance using the ODE pin or per-channel basis, with the LE bit in Backplane Connection Memory. No Connect. These ball-pads MUST remain unconnected. Internal Connect s These inputs MUST be held at logic ‘LOW’. Zarlink Semiconductor Inc. 7 ...
Page 8
... Backplane input to Local output switching. Often a system design does not need to differentiate between Backplane and Local side, and merely needs maximum switching capacity. In this case, the MT90871 can be used as shown in Figure 4 to give the full 8,192 x 8,192 channel capacity. ...
Page 9
... Backplane Connection Memory determines the switching configurations. 2.1.3 Backplane-to-Backplane path The device can provide data switching between the Backplane input and output ports. The Backplane Connection Memory determines the switching configurations. MT90871 Figure Blocking Configuration Zarlink Semiconductor Inc ...
Page 10
... Input stream - Backplane 0-15 (BSTi0-15) Output stream - Backplane 0-15 (BSTo0-15) Table 1- Per-stream Data-Rate Selection: Backplane and Local streams 10 Rate Selection Capability (for each individual stream) 2.048, 4.096, 8.192 or 16.384Mb/s 2.048, 4.096, 8.192 or 16.384Mb/s 2.048, 4.096, 8.192 or 16.384Mb/s 2.048, 4.096, 8.192 or 16.384Mb/s Zarlink Semiconductor Inc. Data Sheet ...
Page 11
... Channel Channel Channel Channel Channel Channel 0 7 Channel 0 0 Zarlink Semiconductor Inc. Channel 255 Channel 255 Channel 127 Channel 127 ...
Page 12
... Local Port Timing Diagram for 2,4,8 and 16Mb/s stream rates, and Figure 7, Backplane Port Timing Diagram for and 16Mb/s stream rates. The MT90871 will automatically detect whether an ST-BUS or a GCI-BUS style frame pulse is being used for the master frame pulse (FP8i). The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL ...
Page 13
... Backplane Frame Pulse Input and Local Frame Pulse Output Alignment The MT90871 accepts a Backplane Frame Pulse (FP8i) and generates the Local Frame Pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant three frame delay for data being switched. For further details of Frame Pulse conditions and options see section 13.1 " ...
Page 14
... Channel Delay, 2 Ch0 Ch126 Ch127 Zarlink Semiconductor Inc. Data Sheet Ch126 Ch127 Ch125 Ch126 ...
Page 15
... Ch255 Ch0 Bit Delay, 1 Ch0 Ch255 Ch255 Zarlink Semiconductor Inc. Ch1 Ch1 Ch1 Ch1 Ch1 ...
Page 16
... Ch0 Bit Delay, 1 Ch0 Ch127 Ch127 Zarlink Semiconductor Inc. Data Sheet Ch1 Ch1 Ch1 Ch1 ...
Page 17
... The input pin LORS selects whether the Local output streams LSTo0-15 are set to high impedance at the output of the MT90871 itself or are always driven (active HIGH or active LOW) and a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-1 signals. Setting LORS to a LOW state will configure the output streams LSTo0-15 to transmit bi-state channel data with per-channel high-impedance determined by external circuits under the control of the LCSTo0-1 outputs ...
Page 18
... The Local Output Enable Bit (LE) of the Local Connection Memory has direct per-channel control on the high- impedance state of the Local Output streams, LSTo0-15. Programming a LOW state will set the stream output of the MT90871 to High Impedance for the duration of the channel period. See section 12.3 "Local Connection Memory Bit Definition", for programming details. ...
Page 19
... Zarlink Semiconductor Inc. 2 4Mb/s 2Mb ...
Page 20
... The input pin BORS selects whether the Backplane output streams BSTo0-15 are set to high impedance at the output of the MT90871 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the BCSTo0-1 signals ...
Page 21
... Data Sheet outputs. Setting BORS to a HIGH state will configure the output streams BSTo0-15 of the MT90871 to invoke a high-impedance output on a per-channel basis. The BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. ...
Page 22
... etc. etc. etc. etc. etc. etc. etc. etc. Ch 254 Ch 127 254 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 Zarlink Semiconductor Inc. Data Sheet Frame Boundary ...
Page 23
... Ch1 etc. etc. etc. etc. Zarlink Semiconductor Inc. Frame Boundary 23 ...
Page 24
... The Backplane Output Enable Bit (BE) of the Backplane Connection Memory has direct per-channel control on the high-impedance state of the Backplane Output streams, BSTo0-15. Programming a LOW state will set the stream output of the MT90871 to High Impedance for the duration of the channel period. See section 12.4 "Backplane Connection Memory Bit Definition", for programming details. ...
Page 25
... Figure 15 - Constant Switch Delay: Examples of different stream rates and routing 6.0 Connection Memory Description The MT90871 incorporates two connection memories, Local Connection Memory and Backplane Connection Memory. 6.1 Local Connection Memory The Local Connection Memory (LCM) is 16-bit wide with 4,096 memory locations to support the Local output port ...
Page 26
... Zarlink Semiconductor Inc. Data Sheet Source Channel No. [7:0] legal values [7:0] legal values [7:0] legal values 0 - 127 [7:0] legal values 0 - 255 ...
Page 27
... To prevent the bus ’hanging’, in the event of the MT90871 not receiving a master clock, the microprocessor port shall complete the DTA handshake when accessed but any data read from the bus will be invalid. ...
Page 28
... The RESET pin must remain low for two input clock cycles (C8i) to guarantee a synchronized reset release. When RESET is applied to the MT90871, the CS line is inhibited and the DTA line may become active through simultaneous microport activity. External gating of the DTA line with CS is recommended to avoid bus conflict in applications incorporating multiple devices with individual reset conditions ...
Page 29
... The MT90871 JTAG interface conforms to the Boundary-Scan IEEE 1149.1 standard. The operation of the boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. The JTAG is intended to be used during the development cycle. The JTAG interface is operational when the MT90871 Core ( powered at typical voltage levels ...
Page 30
... This pin must be held LOW for normal (non-JTAG) device operation. 11.2 TAP Registers The MT90871 uses the public instructions defined in the IEEE 1149.1 standard with the provision of an Instruction Register and three Test Data Registers. 11.2.1 Test Instruction Register The JTAG interface contains a four-bit instruction register ...
Page 31
... Table 10, LCM Bits for Local-to-Local and Backplane-to-Local Switching. Bit LSRC selects the switch configuration for Backplane-to-Local or Local-to-Local. When the per- Description Description Description Set to a default value of 0 Local Data Memory Local Input Channel Data Table 9- Local Data Memory (LDM) Bits Zarlink Semiconductor Inc. 31 ...
Page 32
... BORS pin. When HIGH the channel is active. 12-8 BSAB4-0 Backplane Source Stream Address Bits. The binary value of these 5 bits represents the input stream number. Ignored when BMM is set HIGH. Table 11- BCM Bits for Local-to-Backplane and Backplane-to-Backplane Switching 32 Description Description Zarlink Semiconductor Inc. Data Sheet . ...
Page 33
... Backplane Input Bit rate Register 0, BIBRR0 - Register 15, BIBRR15 012D 013C Backplane Output Bit rate Register 0, BOBRR0 - Register 15, BOBRR15 014D Memory BIST Register, MBISTR H 3FFF Revision control register, RCR H Table 12- Address Map for Register (A14 = 0) Description Register Zarlink Semiconductor Inc. 33 ...
Page 34
... LCSTo0-1 are driven low. When HIGH, the BSTo0-15, LSTo0-15, BCSTo0-1 and LCSTo0-1 are enabled. 34 Description ODE Pin OSB bit Output Control with ODE pin and OSB bit Table 13- Control Register Bits Zarlink Semiconductor Inc. Data Sheet . BSTo0 - 15, LSTo0 - 15 Disable Disable Enable ...
Page 35
... FP8i_b (c) Frame Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i_b FP8i_b (d) Frame Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i_b FP8i_b Figure 17 - Frame Boundary Conditions, ST- BUS Operation Description Frame Boundary Zarlink Semiconductor Inc. 35 ...
Page 36
... The BPE bit is set HIGH, to commence the block programming operation. Programming is completed in one frame period and may be be instigated at any time within a frame.The BPE bit returns to LOW to indicate the block programming function has completed. 36 Frame Boundary Zarlink Semiconductor Inc. Data Sheet ...
Page 37
... A LOW to HIGH transition initializes the Backplane BER generator to the seed value. Clear Bit Error Rate Register for Backplane. A LOW to HIGH transition in this bit resets the Backplane internal bit error counter and the Backplane bit error (BBERR) register to zero. Zarlink Semiconductor Inc ...
Page 38
... A LOW to HIGH transition enables the Local BER transmission. When set LOW, transmission is disabled. BER Mode Select for Local. When set HIGH, a PRBS sequence of length 2 port. When set LOW, a PRBS sequence of length 2 Local port. Zarlink Semiconductor Inc. Data Sheet selected for the selected ...
Page 39
... Local Channel Delay Register The binary value of these bits refers to the channel delay value for the Local input stream. 1 Channel 2 Channels 3 Channels 4 Channels 5 Channels ... ... Zarlink Semiconductor Inc. Description Corresponding Delay Bits LCD7-LCD0 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 ...
Page 40
... Zarlink Semiconductor Inc. Data Sheet Description 1 / bit period LID1 LID0 ...
Page 41
... Name Reset Reserved 0 Reserved BCD(7:0) 0 Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the Backplane input stream Zarlink Semiconductor Inc. LID1 LID0 ...
Page 42
... Reserved 0 Reserved BID(4:0) 0 Backplane Input Bit Delay Register The binary value of these bits refers to the input bit delay value for the Backplane input stream Zarlink Semiconductor Inc. Data Sheet BCD7-BCD0 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 ...
Page 43
... Zarlink Semiconductor Inc. BID1 BID0 ...
Page 44
... Table 26- Backplane Output Advancement Register (BOAR) Bits 44 Reset 0 Reserved 0 Local Output Advancement Register Corresponding Advancement Bits LOA1 Name Reset Reserved 0 Reserved BOA(1:0) 0 Backplane Output Advancement Register Zarlink Semiconductor Inc. Data Sheet Description LOA0 Description ...
Page 45
... The binary value of these bits refers to the Local output stream which carries the BER data. 0 Local BER Send Channel Address Bits. The binary value of these bits refers to the Local output channel in which the BER data starts to be sent. Description Zarlink Semiconductor Inc. Corresponding Advancement Bits BOA1 BOA0 0 0 ...
Page 46
... Local BER Receive Channel Address Bits The binary value of these bits refers to the Local input Start Channel in which the BER data will be received. Description Local Bit Error Rate Count The binary value of the bits define the Local Bit Error count. Zarlink Semiconductor Inc. Data Sheet ...
Page 47
... Start Channel allocated for the BER Transmitter. (i.e. Total Channels = Start Channel + BTXBL value) Reserved. Backplane Receive BER Length Bits The binary value of these bits define the number of channels in addition to the Start Channel allocated for the BER receiver. (i.e. Total Channels = Start Channel + BRXBL value) Zarlink Semiconductor Inc. Description Description Description 47 ...
Page 48
... The binary value of these bits define the Backplane input Start Channel in which the BER data will be received. Description Backplane Bit Error Rate Count The binary value of these bits define the Backplane Bit Error count. Reset 0 Reserved 0 Local Input Bit Rate Zarlink Semiconductor Inc. Data Sheet Description ...
Page 49
... Bit rate for stream 2Mb 4Mb 8Mb 16Mb/s Reset 0 Reserved 0 Local Output Bit Rate LOBR1 LOBR0 Bit rate for stream 2Mb 4Mb 8Mb 16Mb/s Reset 0 Reserved 0 Backplane Input Bit Rate Zarlink Semiconductor Inc. Description Description 49 ...
Page 50
... Sequence enabled on LOW to HIGH transition. Table 46- Memory BIST Register (MBISTR) Bits 50 BIBR0 Bit rate for stream n 0 2Mb/s 1 4Mb/s 0 8Mb/s 1 16Mb/s Reset 0 Reserved 0 Backplane Output Bit Rate BOBR0 Bit rate for stream n 0 2Mb/s 1 4Mb/s 0 8Mb/s 1 16Mb/s Description Zarlink Semiconductor Inc. Data Sheet Description ...
Page 51
... The revision control register stores the binary value of the silicon revision number. This register is read only. The RCR register is configured as follows: Bit Name Reset Value 15-4 Reserved 3-0 RC(3:0) defined by silicon Table 47- Revision Control Register (RCR) Bits Description 0 Reserved. Revision Control Bits. Zarlink Semiconductor Inc. Description 51 ...
Page 52
... I_5V Sym Min T - 3.0 DD_IO V 1.62 DD_CORE V 1.62 DD_PLL I_5V ) unless otherwise stated. Sym Min I DD-Core I DD-Core I DD_IO I DD_IO Zarlink Semiconductor Inc. Data Sheet Min Max -0.5 5.0 -0.5 2.5 -0.5 2.5 -0.5 V +0.5 DD_IO -0.5 7 +125 Typ Max 25 +85 3.3 3.6 1.8 1.98 1.8 1.98 3.3 V DD_IO 5 5.5 Typ Max Units Test Conditions ...
Page 53
... unless otherwise stated. Timing Parameter Measurement: Voltage Levels Sym Level V 0.5V CT DD_IO V 0.7V HM DD_IO V 0.3V LM DD_IO Zarlink Semiconductor Inc. Typ Max Units Test Conditions V 0.8 V µ < V < DD_IO µA 5 µA -200 Input at 0V 200 µA Input at V ...
Page 54
... FPW16 t -29 FODF16 t 30 FODR16 t 62 LCP16 t 29 LCH16 t 30 LCL16 rLC16o t fLC16o Zarlink Semiconductor Inc. Data Sheet Max Units Notes 350 ns Fig. 19 & Fig. 20 220 220 110 ns 110 110 110 ns 110 110 124 ...
Page 55
... Figure 19 - Backplane and Local Clock Timing Diagram for ST-BUS t BFPW244 t BFPH244 t BFPW122 t t BFPS122 BFPH122 t t BCP8 BCH8 t LFBOS t LFPW8_244 t t FODF8_244 FODR8_244 t LFPW8 t t LFODF8 LFODR8 t LCH8 t FPW16 t t FODR16 FODF16 Zarlink Semiconductor Inc rBC8i fBC8i t LCP8 t t rLC8o fLC8o t LCP16 t t fLC16o rLC16o 55 ...
Page 56
... Figure 20 - Backplane and Local Clock Timing for GCI-BUS 56 t BGFPW t t BGFPS BGFPH t BCP8 t t BCH8 BCL8 t t fBCi t LFBOS t GFPW8 t t GFPS8o GFPH8o t t LCH8 LCP8 t FPW16 t FRH16o t LCP16 t rLC16o Zarlink Semiconductor Inc. Data Sheet rBCi t t rLC8o fLC8o t fLC16o ...
Page 57
... Ch0 Ch0 t BIDS4 t BSIS4 t BSIH4 Bit7 Bit6 Ch0 Ch0 t BSOD4 Bit6 Bit7 Ch0 Ch0 t BIDS2 t BSIS2 t Bit7 Ch0 t BSOD2 Bit7 Ch0 Zarlink Semiconductor Inc. Typ Max Units Notes 183 188 366 371 =50pF L 10.5 10.5 10 Bit2 Bit1 ...
Page 58
... BSTo0 - 15 16.384Mb/s * CK_int is the internal clock signal of 131.072MHz Figure 22 - ST-BUS Backplane Data Timing Diagram (16Mb/ BIDS16 t BSIS16 t BSIH16 Bit0 Bit7 Ch0 Ch 255 t BSOD16 Bit0 Bit7 Ch255 Ch0 Zarlink Semiconductor Inc. Data Sheet Bit6 Bit5 Ch0 Ch0 Bit5 Bit6 Ch0 Ch0 ...
Page 59
... BSIS2 Bit0 Ch0 t BSOD2 Bit0 Ch0 t BIDS16 t BSIS16 t BSIH16 Bit0 Bit7 Ch0 Ch255 t BSOD16 Bit7 Bit0 Ch255 Ch0 Zarlink Semiconductor Inc Bit5 Bit6 Bit4 Ch0 Ch0 Ch0 Bit2 Ch0 Bit2 Ch0 t BSIH2 Bit1 Ch0 Bit1 Ch0 Bit1 Bit2 Ch0 ...
Page 60
... LIDS16 LIDS8 t 178 183 188 LIDS4 t 361 366 371 LIDS2 t 2.1 LSIS16 t 2.1 LSIS8 t 2.1 LSIS4 t 2.1 LSIS2 t 3 LSIH16 t 3 LSIH8 t 3 LSIH4 t 3 LSIH2 t 10.5 LSOD16 t 10.5 LSOD8 t 10.5 LSOD4 t 10.5 LSOD2 Zarlink Semiconductor Inc. Data Sheet Units Notes ns C =50pF =50pF L ...
Page 61
... Bit7 Ch0 t LSOD2 Bit7 Ch0 t LFBOS t LIDS16 t LSIS16 t LSIH16 Bit0 Bit7 Ch0 Ch255 t LSOD16 Bit0 Bit7 Ch255 Ch0 Zarlink Semiconductor Inc Bit2 Bit1 Bit3 Ch0 Ch0 Ch0 Bit5 Ch0 Bit5 Bit4 Ch0 Ch0 t LSIH2 Bit6 Ch0 Bit6 Ch0 Bit6 ...
Page 62
... HiZ STo t ZD HiZ Valid Data STo ODE t t ODE ODZ Valid Data STo Hi-Z Hi-Z Figure 28 - Output Driver Enable (ODE) Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns R =1K, C =50pF, See Note =1K, C =50pF, See Note ...
Page 63
... AKH = 1K/1K potential divider, with timing corrected to cancel time taken L t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t DDR t AKD Zarlink Semiconductor Inc. Test Conditions C =60pF L C =60pF, R =1K, Note =60pF L C =60pF L C =60pF, R ...
Page 64
... TOP VIEW NOTES:- 1. Controlling dimensions are in MM. 2. Seating plane is defined by the spherical crown of the solder balls. 3. Not to scale. 4. Ball arrangement array c Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD BOTTOM VIEW SIDE VIEW Previous package codes: DIMENSION ...
Page 65
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...