ADC1415S NXP Semiconductors, ADC1415S Datasheet - Page 32

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ADC1415S

Manufacturer Part Number
ADC1415S
Description
Single 14-bit ADC
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
Table 24.
Table 25.
Table 26.
Table 27.
ADC1415S_SER_3
Preliminary data sheet
Bit
7 to 4
3
2 to 0
Bit
7 to 6
5 to 0
Bit
7 to 3
2 to 0
Bit
7 to 0
Symbol
-
DAVINV
DAVPHASE[2:0]
Symbol
-
DIG_OFFSET[5:0]
Symbol
-
TESTPAT_SEL[2:0]
Symbol
TESTPAT_USER[13:6]
Output clock register (address 0012h) bit description
Offset register (address 0013h) bit description
Test pattern register 1 (address 0014h) bit description
Test pattern register 2 (address 0015h) bit description
Access
R/W
R/W
Access
R/W
Access
R/W
Access
R/W
All information provided in this document is subject to legal disclaimers.
ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs
Value
0000
0
1
000
001
010
011
100
101
110
111
Value
00
011111
...
000000
...
100000
Value
00000
000
001
010
011
100
101
110
111
Value
00000000
Rev. 03 — 12 April 2010
Description
not used
output clock data valid (DAV) polarity
DAV phase select
normal
inverted
output clock shifted (ahead) by 3 ns
output clock shifted (ahead) by 2.5 ns
output clock shifted (ahead) by 2 ns
output clock shifted (ahead) by 1.5 ns
output clock shifted (ahead) by 1 ns
output clock shifted (ahead) by 0.5 ns
default value as defined in timing section
output clock shifted (delayed) by 0.5 ns
Description
not used
digital offset adjustment
...
0
...
Description
not used
digital test pattern select
Description
custom digital test pattern (bits 13 to 6)
+31 LSB
−32 LSB
off
mid scale
−FS
+FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern
‘1010..1010.’
‘010..1010’
ADC1415S series
© NXP B.V. 2010. All rights reserved.
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