ADC1415S NXP Semiconductors, ADC1415S Datasheet - Page 17

• Manufacturer Part Number: ADC1415S
• Description: Single 14-bit ADC
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1415S_SER_3
Preliminary data sheet
11.1.4 Selecting the output data format
11.2.1 Input stage
11.2 Analog inputs
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
The analog input of the ADC1415S supports differential or single-ended input drive.
Optimal performance is achieved using differential inputs. The ADC inputs are internally
biased and need to be decoupled.
The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input
stage, including ElectroStatic Discharge (ESD) protection and circuit and package
parasitics, is shown in
The integrated input buffer offers the following advantages:
Fig 8.
•
•
INM
INP
The kickback effect is avoided - the charge injection and glitches generated by the
S/H input stage are isolated from the input circuitry. So there’s no need for additional
filtering.
The input capacitance is very low and constant over a wide frequency range, which
makes the ADC1415S easy to drive.
Input sampling circuit and input buffer
8
7
All information provided in this document is subject to legal disclaimers.
package
ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs
Figure
Rev. 03 — 12 April 2010
ESD
8.
Table
23) or using pin DFS in Pin control mode (offset
BUFFER
INPUT
Section 11.3
ADC1415S series
parasitics
and
Table 21
R on = 15 Ω
R on = 15 Ω
internal
internal
switch
switch
clock
clock
further details).
© NXP B.V. 2010. All rights reserved.
capacitor
capacitor
sampling
sampling
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4 pF
4 pF
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