ADC1415S NXP Semiconductors, ADC1415S Datasheet - Page 31

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ADC1415S

Manufacturer Part Number
ADC1415S
Description
Single 14-bit ADC
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
Table 21.
Table 22.
Table 23.
ADC1415S_SER_3
Preliminary data sheet
Bit
7 to 4
3
2 to 0
Bit
7 to 2
1 to 0
Bit
7 to 5
4
3
2
1 to 0
Symbol
-
INTREF_EN
INTREF[2:0]
Symbol
-
IB_IBIAS[1:0]
Symbol
-
LVDS_CMOS
OUTBUF
OUTBUS_SWAP
DATA_FORMAT[1:0]
Internal reference control register (address 0008h) bit description
Input buffer control register (address 0010h) bit description
Output data standard control register (address 0011h) bit description
Access
R/W
R/W
Access
R/W
Access
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Value
0000
0
1
000
001
010
011
100
101
110
111
ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs
Value
000000
00
01
10
11
Value
000
0
1
0
1
0
1
00
01
10
11
Rev. 03 — 12 April 2010
Description
not used
programmable internal reference enable
programmable internal reference
disable
active
0 dB (FS = 2 V)
−1 dB (FS = 1.78 V)
−2 dB (FS = 1.59 V)
−3 dB (FS = 1.42 V)
−4 dB (FS = 1.26 V)
−5 dB (FS = 1.12 V)
−6 dB (FS = 1 V)
reserved
Description
not used
input buffer bias current
Description
not used
output data standard: LVDS DDR or CMOS
output buffers enable
output bus swapping
output data format
not used
medium
low
high
CMOS
LVDS DDR
output enabled
output disabled (high Z)
no swapping
output bus is swapped (MSB becomes LSB and vice versa)
offset binary
two’s complement
gray code
offset binary
ADC1415S series
© NXP B.V. 2010. All rights reserved.
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