ADC1415S NXP Semiconductors, ADC1415S Datasheet - Page 23

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ADC1415S

Manufacturer Part Number
ADC1415S
Description
Single 14-bit ADC
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
ADC1415S_SER_3
Preliminary data sheet
11.5.1 Digital output buffers: CMOS mode
11.5 Digital outputs
The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0
(see
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in
OGND/V
Each buffer can be loaded by a maximum of 10 pF.
The output resistance is 50 Ω and is the combination of the an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see
Fig 19. CMOS digital output buffer
Table
DDO
23).
to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core.
All information provided in this document is subject to legal disclaimers.
ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs
DRIVER
LOGIC
Rev. 03 — 12 April 2010
Figure
50 Ω
19. The buffer is powered by a separate
PARASITICS
ESD
ADC1415S series
PACKAGE
005aaa057
© NXP B.V. 2010. All rights reserved.
Table
www.DataSheet4U.com
VDDO
Dx
OGND
30):
23 of 39

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