ADC1415S NXP Semiconductors, ADC1415S Datasheet - Page 18

• Manufacturer Part Number: ADC1415S
• Description: Single 14-bit ADC
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1415S_SER_3
Preliminary data sheet
11.2.2 Transformer
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in
The configuration shown in
both cases, the choice of transformer will be a compromise between cost and
performance.
Fig 9.
Fig 10. Dual transformer configuration suitable for high intermediate frequency
Single transformer configuration suitable for baseband applications
application
Analog
input
All information provided in this document is subject to legal disclaimers.
Analog
ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs
input
100 nF
Figure 9
Rev. 03 — 12 April 2010
100 nF
100 nF
ADT1-1WT
Figure 10
100 nF
ADT1-1WT
would be suitable for a baseband application.
100 nF
is recommended for high frequency applications. In
50 Ω
50 Ω
ADT1-1WT
100 nF
ADC1415S series
50 Ω
100 Ω
100 nF
100 nF
100 nF
100 nF
100 nF
005aaa108
100 nF
VCM
INM
INP
005aaa109
© NXP B.V. 2010. All rights reserved.
VCM
INM
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INP
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