ADC1415S NXP Semiconductors, ADC1415S Datasheet - Page 20

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ADC1415S

Manufacturer Part Number
ADC1415S
Description
Single 14-bit ADC
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
ADC1415S_SER_3
Preliminary data sheet
Fig 12. Internal reference, 2 V (p-p) full scale
Fig 14. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
11.3.2 Reference gain control
11.3.3 Common-mode output voltage (V
V
330 pF
SENSE
VREF
VDDA
0.1 μF
SENSE
Figure 12
required reference voltage source.
The reference gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see
Table
1 V (p-p), as shown in
Table 12.
A 0.1 μF filter capacitor should be connected between pin VCM and ground.
VREF
INTREF
000
001
010
011
100
101
110
111
EQUIVALENT
REFERENCE
SCHEMATIC
21). The corresponding full-scale input voltage range varies between 2 V (p-p) and
REFERENCE
EQUIVALENT
SCHEMATIC
to
Reference SPI Gain Control
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Figure 15
005aaa119
All information provided in this document is subject to legal disclaimers.
ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs
Table
illustrate how to connect the SENSE and VREF pins to select the
Rev. 03 — 12 April 2010
Gain
0 dB
−1 dB
−2 dB
−3 dB
−4 dB
−5 dB
−6 dB
reserved
12:
Fig 13. Internal reference, 1 V (p-p) full scale
Fig 15. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
O(cm)
full-scale
)
330 pF
330
pF
full scale (p-p)
2 V
1.78 V
1.59 V
1.42 V
1.26 V
1.12 V
1 V
x
ADC1415S series
SENSE
SENSE
VREF
VREF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
005aaa117
005aaa118
© NXP B.V. 2010. All rights reserved.
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