ADC1415S NXP Semiconductors, ADC1415S Datasheet - Page 28

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ADC1415S

Manufacturer Part Number
ADC1415S
Description
Single 14-bit ADC
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
ADC1415S_SER_3
Preliminary data sheet
Fig 23. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 24. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
(CMOS LVDS DDR)
(CMOS LVDS DDR)
All information provided in this document is subject to legal disclaimers.
ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs
SDIO
SDIO
CS
CS
Rev. 03 — 12 April 2010
Offset binary, LVDS DDR
default mode at start-up
two's complement, CMOS
default mode at start-up
ADC1415S series
© NXP B.V. 2010. All rights reserved.
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