ADC1415S NXP Semiconductors, ADC1415S Datasheet

ADC1415S

Manufacturer Part Number

ADC1415S

Description

Single 14-bit ADC

Manufacturer

NXP Semiconductors

Datasheet

1.ADC1415S.pdf (39 pages)

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1. General description

2. Features and benefits

The ADC1415S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performances and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1415S is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,

thanks to a separate digital output supply.

The ADC1415S supports the Low Voltage Differential Signalling (LVDS) Double Data

Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the

user to easily configure the ADC.

The device also includes a SPI programmable full-scale to allow flexible input voltage

range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the

baseband to input frequencies of 170 MHz or more, the ADC1415S is ideal for use in

communications, imaging and medical applications - especially in high Intermediate

Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures

that the input impedance remains constant and low and the performance consistent over

a wide frequency range.

ADC1415S series

Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps

with input buffer; CMOS or LVDS DDR digital outputs

Rev. 03 — 12 April 2010

SNR, 72 dBFS / SFDR, 86 dBc

Sample rate up to 125 Msps

14-bit pipelined ADC core

Clock input divider by 2 for less jitter

contribution

Integrated input buffer

Flexible input voltage range: 1 V (p-p) to

2 V (p-p)

CMOS or LVDS DDR digital outputs

Pin compatible with the ADC1215S

series, ADC1015S series and the

ADC1115S125

HVQFN40 package

Input bandwidth, 600 MHz

Power dissipation, 635 mW at 80 Msps,

including analog input buffer

SPI

Duty cycle stabilizer

Fast OuT of Range (OTR) detection

INL ±1.5 LSB, DNL ±0.5 LSB

Offset binary, two’s complement, gray

code

Power-down and Sleep modes

Preliminary data sheet

www.DataSheet4U.com

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