MT57V256H36E Micron Semiconductor Products, Inc., MT57V256H36E Datasheet - Page 5

• Manufacturer Part Number: MT57V256H36E
• Description: 9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined
• Manufacturer: Micron Semiconductor Products, Inc.

Table 3:
256K x 36 2.5V V
MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03
SYMBOL
NC/SA
V
R/W#
TMS
DQ_
TDO
V
SA0
SA1
LD#
TCK
V
TDI
V
SA
K#
ZQ
DD
NC
C#
K
C
REF
DD
SS
Q
DD
, HSTL, Pipelined DDR SRAM
Output
Output
Supply
Supply
Supply
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Ball Descriptions
–
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. See Ball Assignment figures for address expansion inputs. SA0 and SA1
are used as the lowest two address bits for BURST READ and BURST WRITE operations. These inputs
are ignored when device is deselected or once BURST operation is in progress.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This
definition includes address and read/write direction. All transactions operate on a burst of four data
(two clock periods of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when
R/W# is HIGH, WRITE when R/W# is LOW) for the loaded address. R/W# must meet the setup and
hold times around the rising edge of K.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
Output Clock: This clock pair provides a user-controlled means of tuning device output data. The
rising edge of C# is used as the output reference for second and fourth output data. The rising edge
of C is used as the output timing reference for first and third output data. Ideally, C# is 180 degrees
out of phase with C. C and C# may be tied HIGH to force the use of K and K# as the output reference
clocks instead of having to provide C and C# clocks. If tied HIGH, C and C# must remain HIGH and not
be toggled during device operation.
IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These balls may be left as No Connects if the
JTAG function is not used in the circuit.
IEEE 1149.1 Clock Input: JEDEC-standard 2.5V I/O levels. This ball must be tied to V
function is not used in the circuit.
HSTL Input Reference Voltage: Nominally V
Output Impedance Matching Input: This input is used to tune the device outputs to the system data
bus impedance. DQ and CQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this ball
to ground. Alternately, this ball can be connected directly to V
impedance mode. This ball cannot be connected directly to GND or left unconnected.
Synchronous Data I/Os: Input data must meet setup and hold times around the rising edges of K and
K#. Output data is synchronized to the respective C and C# data clocks or to K and K# if C and C# are
tied HIGH. See Ball Assignment figures for ball site location of individual signals.
IEEE 1149.1 Test Output: JEDEC-standard 2.5V I/O level.
Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. See DC Electrical Characteristics and
Operating Conditions for range.
Power Supply: GND.
No Connect: These signals may be connected to ground to improve package heat dissipation.
For upgrade to 18, 36, 72, and 144Mb DDR devices, balls 2A, 3A, 9A, and 10A are reserved for
higher-order address bits, respectively.
These balls are reserved for higher-order address bits, respectively.
0.16µm Process
2.5V V
5
DD
DD
Q/2. Provides a reference voltage for the input buffers.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, HSTL, PIPELINED DDR SRAM
DD
Q, which enables the minimum
256K x 36
SS
©2003, Micron Technology Inc.
if the JTAG
ADVANCE