MT57V256H36E Micron Semiconductor Products, Inc., MT57V256H36E Datasheet - Page 14

• Manufacturer Part Number: MT57V256H36E
• Description: 9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined
• Manufacturer: Micron Semiconductor Products, Inc.

NOTE:
Performing A TAP Reset
for five rising edges of TCK. This RESET does not affect
the operation of the SRAM and may be performed
while the SRAM is operating.
that TDO comes up in a High-Z state.
TAP Registers
balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register at a time can be
selected through the instruction register. Data is seri-
ally loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.
Instruction Register
the instruction register. This register is loaded when it
is placed between the TDI and TDO balls, as shown in
Figure 8. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state, as described in the previous section.
the two LSBs are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test
data path.
256K x 36 2.5V V
MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03
TMS
TCK
TDI
X = 68 for the x36 configuration.
A RESET is performed by forcing TMS HIGH (V
At power-up, the TAP is reset internally to ensure
Registers are connected between the TDI and TDO
Three-bit instructions can be serially loaded into
When the TAP controller is in the Capture-IR state,
TAP Controller Block Diagram
DD
Selection
Circuitry
, HSTL, Pipelined DDR SRAM
TAP CONTROLLER
Boundary Scan Register
Figure 8:
31
Identification Register
x
30
Instruction Register
.
29
.
Bypass Register
.
.
.
.
.
.
2
2
2
1
1
1
0
0
0
0
Selection
Circuitry
0.16µm Process
TDO
DD
2.5V V
)
14
Bypass Register
isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with mini-
mal delay. The bypass register is set LOW (V
the BYPASS instruction is executed.
Boundary Scan Register
input and bidirectional balls on the SRAM. Several no
connect (NC) balls are also included in the scan regis-
ter to reserve balls. The SRAM has a 69-bit-long regis-
ter.
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift- DR state. The EXTEST, SAMPLE/PRELOAD, and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.
which the bits are connected. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.
Identification (ID) Register
bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.
Tap Instruction Set
Overview
three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
DD
To save time when serially shifting data through reg-
The boundary scan register is connected to all the
The boundary scan register is loaded with the con-
The Boundary Scan Order table shows the order in
The ID register is loaded with a vendor-specific, 32-
Eight different instructions are possible with the
The TAP controller used in this SRAM is not fully
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, HSTL, PIPELINED DDR SRAM
256K x 36
©2003, Micron Technology Inc.
ADVANCE
SS
) when