MT57V256H36E Micron Semiconductor Products, Inc., MT57V256H36E Datasheet

MT57V256H36E

Manufacturer Part Number

MT57V256H36E

Description

9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT57V256H36E.pdf (21 pages)

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9Mb

DDR SRAM

FEATURES

• Fast cycle times: 5ns and 6ns

• 256K x 36 configuration

• Pipelined, double data rate operation

• Single +2.5V ±0.1V power supply (V

• Separate isolated output buffer supply (V

• JEDEC-standard HSTL I/O

• User-selectable trip point with V

• HSTL programmable impedance outputs

• Echo clock outputs

• JTAG boundary scan

• Fully-static design for reduced-power standby

• Clock-stop capability

• Common data inputs and data outputs

• Low-control ball count

• Internally self-timed, registered LATE WRITE cycles

• Linear burst order with four-tick burst counter

• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

• Full data coherency, providing most current data

NOTE:

256K x 36 2.5V V

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

OPTIONS

• Clock Cycle Timing

• Configurations

• Package

1. A Part Marking Guide for the FBGA devices can be found on

‡

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

synchronized to optional dual-data clocks

package

Micron’s Web

5ns (200 MHz)

6ns (167 MHz)

256K x 36

165-ball, 13mm x 15mm FBGA

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

, HSTL, Pipelined DDR SRAM

site—http://www.micron.com/numberguide.

REF

MT57V256H36E

MARKING

)

-5

-6

0.16µm Process

2.5V V

Table 1:

General Description

high-speed, low-power CMOS designs using an

advanced 6T CMOS process.

advanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through

registers controlled by an input clock pair (K and K#)

and are latched on the rising edge of K and K#. The

synchronous inputs include all addresses, all data

inputs, active LOW load (LD#) and read/write (R/W#).

Write data is registered on the rising edges of both K

and K#. Read data is driven on the rising edge of C and

C# if provided, or on the rising edge of K and K#, if C

and C# are not provided.

(ZQ). Synchronous data outputs (Q) are closely

matched to the two echo clocks (CQ and CQ#), which

can be used as data receive clocks. Output data clocks

(C, C#) are also provided for maximum system clock-

ing and data synchronization flexibility.

MT57V256H36E

PART NUMBER

MT57V256H36EF-xx

The Micron

The DDR SRAM integrates a 9Mb SRAM core with

Asynchronous inputs include impedance match

Micron Technology, Inc., reserves the right to change products or specifications without notice.

, HSTL, PIPELINED DDR SRAM

Valid Part Numbers

165-Ball FBGA

DDR synchronous SRAM employs

Figure 1:

DESCRIPTION

256K x 36, HSTL, DDR, Pipelined

256K x 36

ADVANCE

‡

Related parts for MT57V256H36E

MT57V256H36E Summary of contents

Page 1

... V , HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. ...

Page 2

... The functional block diagram illustrates simplified device operation. See truth tables, ball descriptions, and timing diagrams for detailed information and CQ# do not tri-state except during some JTAG test modes. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. Please refer to Micron’s Web site sramds) for the latest data sheet. ...

Page 3

... ASIC) Source CLK Return CLK# Source CLK 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM 175 W to 350 W . Alternately, the ZQ ball can be connected directly to V device in a minimum impedance mode. Output impedance updates may be required because variations may occur in supply voltage and temperature over time ...

Page 4

... DQ33 DQ35 R TDO TCK SA NOTE: 1. Expansion address: 2A for 144Mb 2. Expansion address: 3A for 36Mb 3. Expansion address: 9A for 18Mb 4. Expansion address: 10A for 72Mb 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. R/ SA0 ...

Page 5

... For upgrade to 18, 36, 72, and 144Mb DDR devices, balls 2A, 3A, 9A, and 10A are reserved for higher-order address bits, respectively. NC/SA These balls are reserved for higher-order address bits, respectively. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD Q/2. Provides a reference voltage for the input buffers Micron Technology, Inc ...

Page 6

... SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 4. 2. State transitions (LD# = LOW (LD# = HIGH (R/W# = HIGH (R/W# = LOW). 3. State machine control timing sequence is controlled by K. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD THIRD ADDRESS (INTERNAL) X ...

Page 7

... It is recommended that when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD LD# R/W# ...

Page 8

... AC Electrical Characteristics And Operating Conditions Notes appear following parameter tables; 0ºC £ T DESCRIPTION CONDITIONS Input High (Logic 1) Voltage Input Low (Logic 0) Voltage 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. ABSOLUTE MAXIMUM RATINGS Voltage on V Voltage on V Relative ...

Page 9

... Table 10: Thermal Resistance Note 14; notes appear following parameter tables DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Balls (Bottom) 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. 0ºC £ T £ +70º MAX unless otherwise noted DD A CONDITIONS SYMBOL ³ ...

Page 10

... Data-in valid rising edge Hold Times K rising edge to address hold K rising edge to control inputs hold K, K# rising edge to data-in hold 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD £ +70°C; +2.4V £ SYMBOL ...

Page 11

... Operating supply currents and burst mode cur- rents are calculated with 50 percent READ cycles and 50 percent WRITE cycles. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. 12. NOP currents are valid when entering NOP after ...

Page 12

... Outputs are disabled (High-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high-clock frequencies it may be required to prevent bus contention. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. Q/2 DD Figure 6: ...

Page 13

... TCK allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD TAP Controller State Diagram TEST-LOGIC ...

Page 14

... LSBs are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. Bypass Register To save time when serially shifting data through reg- ...

Page 15

... The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1-compliant. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in ...

Page 16

... CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 10. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD Figure 9: TAP Timing ...

Page 17

... IL AC £ +2.6 and V Power-up During normal operation must not exceed widths less than KHKL (MIN) or operate at frequencies exceeding 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. 2.5V SS CONDITIONS SYMBOL £ V £ ...

Page 18

... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD 256K x 36 DESCRIPTION 000 Reserved for version number ...

Page 19

... DQ14 26 DQ15 27 DQ16 28 DQ17 GND/SA20 31 NC/SA18 SA1 34 SA0 35 LD# 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD BALL 10P 11P 11N 10M 11M 11L 10K 11K 11J ...

Page 20

... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. Figure 11: 165-Ball FBGA ...

Page 21

... Removed I (Stop Clock Current) from I SB • New ADVANCE data sheet for 0.16µm process, Rev. A, Pub. 10 /02 .....................................................................10/02 256K HSTL, Pipelined DDR SRAM DD MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03 0.16µm Process 2. HSTL, PIPELINED DDR SRAM DD table DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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