WM8753 Wolfson Microelectronics plc, WM8753 Datasheet - Page 62

• Manufacturer Part Number: WM8753
• Description: HI FI AND TELEPHONY DUAL CODEC
• Manufacturer: Wolfson Microelectronics plc

Advanced Information
w
READEN=0
READEN=1
GPIO5/CSB
GPIO5/CSB
SDOUT
SCLK
SCLK
SDIN
SDIN
Table 58 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
GPIO5/CSB latches in a complete control word consisting of the last 16 bits.
In 3-wire mode readback is also available to allow read of a device ID register or interrupt status
registers. Readback is enabled by setting READEN. The address of the register to be read back is
selected by setting READSEL[2:0]. The readback data can be output on ADCDAT by setting RDDAT
or on GPI/CLK1, GP2/CLK2, GPIO3 or GPIO4 by configuring the GPIO pins using control bits
GP1M[1:0], GP2M[1:0], GP3M[2:0] and GP4M[2:0].
The SDOUT virtual pin will be tri-state when the CSB pin is high, allowing data from multiple sources
to be connected to the same controller.
Figure 24 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8753L supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit
address of each register in the WM8753L).
The WM8753L operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8753L, then the WM8753L responds by pulling SDIN low on the next clock pulse
(ACK). If the address is not recognised or the R/W bit is ‘1’ when operating in write only mode, the
WM8753L returns to the idle condition and wait for a new start condition and valid address.
During a write, once the WM8753L has acknowledged a correct address, the controller sends the first
byte of control data (B15 to B8, i.e. the WM8753L register address plus the first bit of register data).
The WM8753L then acknowledges the first data byte by pulling SDIN low for one clock pulse. The
controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register
data), and the WM8753L acknowledges again by pulling SDIN low.
Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a
complete sequence the WM8753L returns to the idle state and waits for another start condition. If a
start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN
changes while SCLK is high), the device jumps to the idle condition.
SDOUT tri-stated when CSB=1
MODE/GPIO3
S7
B15
B15
High
Low
B14
B14
S6
control register address
B13
B13
S5
status word
B12
B12
S4
B11
B11
S3
B10
B10
S2
INTERFACE FORMAT
B9
B9
S1
B8
B8
S0
2 wire
3 wire
B7
B7
S7
B6
B6
S6
control register data
B5
B5
S5
status word (duplicated)
B4
B4
S4
B3
B3
S3
B2
B2
S2
B1
B1
S1
B0
B0
S0
latch
latch
AI Rev 3.1 June 2004
WM8753L
62