WM8753 Wolfson Microelectronics plc, WM8753 Datasheet - Page 60

• Manufacturer Part Number: WM8753
• Description: HI FI AND TELEPHONY DUAL CODEC
• Manufacturer: Wolfson Microelectronics plc

Advanced Information
w
PMS selects Voice audio interface operation in master or slave mode. In Master mode VXCLK and
VXFS are outputs. The frequency of FS is set by the sample rate control bits SRMODE and PSR. In
Slave mode VXCLK and VXFS are inputs.
Table 55 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data.
R3 (03h)
Digital Voice
Audio
Interface
Format
REGISTER
ADDRESS
8
7
6
5
4
3:2
1:0
BIT
ADCDOP
VXCLKINV
PMS
MONO
PLRP
PWL[1:0]
PFORMAT[1:
0]
LABEL
0
0
0
0
0
10
10
DEFAULT
ADC data output to ADCDAT and
VXDOUT enable
0 = ADC data output to ADCDAT or
VXDOUT as selected by IFMODE[1:0]
1 = ADC data output to ADCDAT and
VXDOUT
VXCLK invert bit (for master and slave
modes)
0 = VXCLK not inverted
1 = VXCLK inverted
Voice Interface Master / Slave Mode
Control
1 = Enable Master Mode
0 = Enable Slave Mode
Mono ADC data only
1 = output left channel ADC data only
0 = output left and right ADC data
Vx DAC and ADC right, left and I
modes VXCLK polarity
1 = invert VXCLK polarity
0 = normal VXCLK polarity
Vx DAC and ADC DSP Mode – mode
A/B select
1 = MSB is available on 1
edge after VXFS rising edge (mode B)
0 = MSB is available on 2
rising edge after VXFS rising edge
(mode A)
Vx DAC and ADC Audio Data Word
Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
Vx DAC and ADC Audio Data Format
Select
11 = DSP Mode
10 = I
01 = Left justified
00 = Right justified
2
S Format
DESCRIPTION
AI Rev 3.1 June 2004
st
nd
WM8753L
VXCLK rising
VXCLK
2
S
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