WM8753 Wolfson Microelectronics plc, WM8753 Datasheet - Page 61

• Manufacturer Part Number: WM8753
• Description: HI FI AND TELEPHONY DUAL CODEC
• Manufacturer: Wolfson Microelectronics plc

WM8753L
CONTROL INTERFACE
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Table 56 Audio Interface Control
Control bits VXCLKTRI, BCLKTRI, VXDTRI and ADCDTRI configure the Hi-Fi and Voice
interface pins BCLK, VXCLK, ADCDAT and VXDOUT as inputs or tristate. This allows the I
and PCM interfaces to be connected to an interface bus and all outputs onto the bus tristated
or switched to inputs. The default state for all audio interface PMS is input or tristate.
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE/GPIO3 pin is
sampled at power-up, latched and used to select the interface format. After power-up MODE/GPIO3
is available for general purpose use. The CSB/GPIO5 pin is also sampled and latched on power-up
and, if 2-wire mode is selected, the latched value selects the 2-wire mode address. For 3-wire mode
CSB/GPIO5 is always an input. After power-up in 2-wire mode CSB/GPIO5 is available for general
purpose use. See MODE/GPIO3 and CSB/GPIO5 LATCH on Power-up Timing Information on page
9.
The WM8753L is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control
register.
Table 57 PCM and Hi-Fi Interface Tristate
R5 (05h)
Digital
Interface
Control
R5 (05h)
Digital Audio
Interface
Control
REGISTER
REGISTER
ADDRESS
ADDRESS
Audio
3:2
1
0
7
6
5
4
BIT
BIT
IFMODE [1:0]
VXFSOE
LRCOE
VXCLKTRI
BCLKTRI
VXDTRI
ADCDTRI
LABEL
LABEL
00
1
1
0
0
1
1
DEFAULT
DEFAULT
Interface mode
00 = Voice Codec + HiFi DAC.
01 = Voice Codec on HiFi interface.
10 = HiFi over HiFi interface.
11 = HiFi over HiFi interface, using
VXFS for ADC frame sync.
Configures direction of VXFS pin in
master mode
0 = Pin is input
1 = Pin is output
Configures direction of LRC pin in
master mode
0 = Pin is input
1 = Pin is output
VXCLK tristate
0 = VXCLK pin configured as input or
output as set by PMS
1 = VXCLK pin tristated and used as
input
BCLK tristate
0 = BCLK pin configured as input or
output as set by MS
1 = BCLK pin tristated and used as input
VXDOUT tristate
0 = VXDOUT pin enabled as output
1 = VXDOUT pin tristated
ADCDAT tristate
0 = ADCDAT pin enabled as output
1 = ADCDAT pin tristated
DESCRIPTION
DESCRIPTION
AI Rev 3.1 June 2004
Advanced Information
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