WM8753 Wolfson Microelectronics plc, WM8753 Datasheet - Page 45

• Manufacturer Part Number: WM8753
• Description: HI FI AND TELEPHONY DUAL CODEC
• Manufacturer: Wolfson Microelectronics plc

WM8753L
w
Table 42 Analogue Output Control
OUT4 OUTPUT
The OUT4 output can be used to output a buffered Vmid for driving a mono or stereo headset in
capless mode, output the signal from the record mixer or drive out an inverted LOUT2 signal. The
output mode is determined by OUT4SW[1:0]. This output is enabled by setting register bit OUT4 high.
ZERO CROSS TIMEOUT
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output
pgas the gain will automatically update after a timeout period if a zero cross has not occurred. This is
enabled by setting TOEN. The timeout period is dependent on the clock input to the digital and is
equal to 2
pcmclk using SLWCLK..
Table 41 Timeout Clock Controls
ENABLING THE OUTPUTS
Each analogue output of the WM8753L can be separately enabled or disabled. The analogue mixer
associated with each output is powered on or off along with the output pin. All outputs are disabled by
default. To save power, unused outputs should remain disabled.
Outputs can be enabled at any time, except when VREF is disabled (VR=0), as this may cause pop
noise (see “Power Management” and “Applications Information” sections)
Table 40 OUT4SW control of OUT4
R63 (3Fh)
Additional
Control
R18 (12h)
Additional
Control
R52 (34h)
Clock Control
R22 (16h)
Power
Management
(3)
Note: All “Enable” bits are 1 = ON, 0 = OFF
REGISTER
REGISTER
REGISTER
ADDRESS
ADDRESS
ADDRESS
21
* input clock period. The timeout clock may be set to be derived from either the mclk or
8:7
0
0
8
7
6
5
4
3
2
1
BIT
BIT
BIT
OUT4SW
[1:0]
TOEN
SLWCLK
LOUT1
ROUT1
LOUT2
ROUT2
OUT3
OUT4
MONO1
MONO2
LABEL
LABEL
LABEL
00
0
0
0
0
0
0
0
0
0
0
DEFAULT
DEFAULT
DEFAULT
OUT4 Output select
00 = VREF
01 = Record Mixer
10 = LOUT2 signal
11 = unused
Timeout clock enable
0 = timeout clock disabled
1 = timeout clock enabled
Timeout and Headphone switch clock
source
0 = mclk
1 = pcm clk
LOUT1 Enable
ROUT1 Enable
LOUT2 Enable
ROUT2 Enable
OUT3 Enable
OUT4 Enable
MONO1 Enable
MONO2 Enable
(volume controlled by LOUT2VOL)
DESCRIPTION
DESCRIPTION
DESCRIPTION
AI Rev 3.1 June 2004
Advanced Information
45