MCIMX27 Motorola Semiconductor Products, MCIMX27 Datasheet - Page 7

• Manufacturer Part Number: MCIMX27
• Manufacturer: Motorola Semiconductor Products

Freescale Semiconductor
Block Mnemonic
SAHARA2
PCMCIA
MSHC
LCDC
PWM
M3IF
RTIC
MAX
NFC
RTC
PLL
Multi-layer AHB
Host Controller
Liquid Crystal
Memory Stick
Memory Card
Block Name
Multi-Master
NAND Flash
International
Hashing and
Pulse-Width
Asymmetric
Association
Phase Lock
Symmetric/
Accelerator
Modulator
Real Time
Controller
Controller
Computer
Run-Time
Checkers
Crossbar
Interface
Personal
Random
Memory
Integrity
Display
Switch
Clock
Loop
Table 2. Digital and Analog Modules (continued)
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Reset Control
Connectivity
Bus Control
Functional
Multimedia
Grouping
Peripheral
Peripheral
Peripheral
Preliminary—Subject to Change Without Notice
Clock and
Interface
Interface
Interface
Interface
External
External
External
Memory
Memory
Memory
Security
Security
Timer
Timer
The LCDC provides display data for external gray-scale or
color LCD panels.
The M3IF controls memory accesses from one or more
masters through different port interfaces to different external
memory controllers ESDCTL/MDDRC, PCMCIA, NFC, and
WEIM.
The ARM926EJ-S processor’s instruction and data buses and
all alternate bus master interfaces arbitrate for resources via a
6 × 3 MAX. There are six fully functional master ports (M0–M5)
and three fully functional slave ports (S0–S2). The MAX is
uni-directional. All master and slave ports are AHB-Lite
compliant.
The MSHC is placed in between the AIPI and the customer
memory stick to support data transfer from the i.MX27 device
to the customer memory stick.
The NFC is a submodule of EMI. The NFC implements the
interface to standard NAND Flash memory devices.
The PCMCIA host adapter module provides the control logic
for PCMCIA socket interfaces, and requires some additional
external analog power switching logic and buffering.
The two DPLLs provide clock generation in digital and mixed
analog/digital chips designed for wireless communication and
other applications.
The PWM has a 16-bit counter and is optimized to generate
sound from stored sample audio images. It can also generate
tones.
The RTC module provides a current stamp of seconds,
minutes, hours, and days. Alarm and timer functions are also
available for programming. The RTC supports dates from the
year 1980 to 2050.
The RTIC ensures the integrity of the contents of the peripheral
memory and assists with boot authentication.
SAHARA2 is a security co-processor which forms part of the
Platform Independent Security Architecture (PISA), and can be
used on cell phone baseband processors or wireless PDAs.
Functional Description and Application Information
Brief Description
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