MCIMX27 Motorola Semiconductor Products, MCIMX27 Datasheet - Page 16

• Manufacturer Part Number: MCIMX27
• Manufacturer: Motorola Semiconductor Products

Functional Description and Application Information
2.3.14
The general-purpose input/output (GPIO) module provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When it is configured as an output, you can write to an internal
register to control the state driven on the output pin. When configured as an input, you can detect the state
of the input by reading the state of an internal register. The GPIO includes all of the general purpose
input/output logic necessary to drive a specific data to the pad and control the direction of the pad using
registers in the GPIO module. The ARM926 is able to sample the status of the corresponding pads by
reading the appropriate status register. The GPIO supports up to 32 interrupts and has the ability to identify
interrupt edges as well as generate three active high interrupts.
2.3.15
The i.MX27 processor contains six identical 32-bit General Purpose Timers (GPT) with programmable
prescalers and compare and capture registers. Each timer’s counter value can be captured using an external
event, and can be configured to trigger a capture event on the rising or/and falling edges of an input pulse.
Each GPT can also generate an event on the TOUT pin, and an interrupt when the timer reaches a
programmed value. Each GPT has an 11-bit prescaler that provides a programmable clock frequency
derived from multiple clock sources, including ipg_clk_32k, ipg_clk_perclk, ipg_clk_perclk/4, and
external clock from the TIN pin. The counter has two operation modes: free-run and restart mode. The GPT
can work in low-power mode.
2.3.16
Inter IC Communication (I
method of data exchange, minimizing the interconnection between devices. This bus is suitable for
applications requiring occasional communications over a short distance between many devices. The
flexible I
The I
to Phillips I
arbitration and collision detection that prevents data corruption if multiple devices attempt to control the
bus simultaneously. This feature supports complex applications with multiprocessor control and can be
used for rapid testing and alignment of end products through external connections to an assembly-line
computer.
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2
C operates up to 400 kbps dependent on pad loading and timing. (For pad requirement details, refer
— Interpreting buffer descriptors
— Address recognition for receive frames
— Random number generation for transmit collision backoff timer
The Message Information Block (MIB) in FEC maintains counters for a variety of network events
and statistics. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and
some of the IEEE 802.3 counters.
2
C enables additional devices to be connected to the bus for expansion and system development.
2
General Purpose I/O Module (GPIO)
General Purpose Timer (GPT)
Inter IC Communication (I
C Bus Specification, Version 2.1.) The I
2
C) is a two-wire, bidirectional serial bus that provides a simple, efficient
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Preliminary—Subject to Change Without Notice
2
C)
2
C system is a true multiple-master bus, including
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