MCIMX27 Motorola Semiconductor Products, MCIMX27 Datasheet - Page 4

• Manufacturer Part Number: MCIMX27
• Manufacturer: Motorola Semiconductor Products

Functional Description and Application Information
1.3
Table 1
2
2.1
The ARM926 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6 × 3 Multi-Layer AHB
crossbar switch (MAX), and a “primary AHB” complex.
Four alternate bus master interfaces are connected to MAX Master Ports 2–5. Three slave ports of the
MAX are AHB-Lite compliant buses. Slave Port 0 is designated as the “primary” AHB. The primary AHB
is internal to the platform and has five slaves connected to it: the AITC interrupt module, the MCTL
memory controller, and two AIPI peripheral interface gaskets. Slave Ports 1 and 2 of the MAX are referred
to as “secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform.
The ARM926EJ-S processor supports the 32-bit and 16-bit ARM Thumb instruction sets, enabling the
user to trade off between high performance and high-code density. The ARM926EJ-S processor includes
features for efficient execution of Java byte codes, providing Java performance similar to the just-in-time
(JIT) compiler—which is a type of Java compiler—but without the associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debugging. The ARM926EJ-S processor has a Harvard cached architecture and
provides a complete high-performance processor subsystem, including the following:
The ARM926EJ-S processor provides support for external coprocessors enabling floating-point or other
application-specific hardware acceleration to be added. The ARM926EJ-S processor implements ARM
architecture version 5TEJ.
The four alternate bus master ports on the ARM926 Platform, which are connected directly to master ports
of the MAX, are designed to support connections to multiple AHB masters external to the platform. An
external arbitration AHB control module is needed if multiple external masters are desired to share an
ARM926 Platform alternate bus master port. However, the alternate bus master ports on the platform
support seamless connection to a single master with no external interface logic required.
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Functional Description and Application Information
The instruction bus (I-AHB) of the ARM926EJ-S processor is connected directly to MAX Master
Port 0.
The data bus (D-AHB) of the ARM926EJ-S processor is connected directly to MAX Master Port 1.
An ARM9EJ-S integer core
A Memory Management Unit (MMU)
Separate instruction and data AMBA AHB bus interfaces
ETM and JTAG-based debug support
provides ordering information for the MAPBGA, lead-free packages.
Ordering Information
ARM926 Microprocessor Core Platform
MCIMX27VOP4
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Device
Preliminary—Subject to Change Without Notice
Table 1. Ordering Information
–20 °C to +85 °C
Temperature
Package
1816-01
Freescale Semiconductor