MCIMX27 Motorola Semiconductor Products, MCIMX27 Datasheet - Page 50

• Manufacturer Part Number: MCIMX27
• Manufacturer: Motorola Semiconductor Products

Signal Descriptions
3.5.3.1
These are the general timing requirements for the ATA interface signals.
NOTE:
3.5.4
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSI, SAP) and external serial interfaces (audio and voice codecs). The AC timing
of AUDMUX external pins is hence governed by SSI and SAP modules. Please refer to their respective
electrical specifications.
3.5.5
This section describes the electrical information (AC timing) of the CSI.
3.5.5.1
VSYNC, HSYNC, and PIXCLK signals are used in this mode. A frame starts with a rising/falling edge on
VSYNC, then HSYNC goes high and holds for the entire line. The pixel clock is valid as long as HSYNC
is high.
parameters.
50
SI1
SI2
SI3
amplitude with all capacitive loads from 15 pf through 40 pf where all signals have the same capacitive load value.
ID
ATA Interface Signals
SRISE and SFALL meets this requirement when measured at the sender’s connector from 10–90% of full signal
Rising edge slew rate for any signal on ATA
interface (see note)
Falling edge slew rate for any signal on ATA
interface (see note)
Host interface signal capacitance at the host
connector
Figure 9
Digital Audio Mux (AUDMUX)
CMOS Sensor Interface (CSI)
General Timing Requirements
Gated Clock Mode Timing
and
Figure 10
Parameter
Table 19. AC Characteristics of All Interface Signals
Figure 8. ATA interface Signals Timing Diagram
i.MX27 Data Sheet, Advance Information, Rev. 0.1
depict the gated clock mode timings of CSI, and
Preliminary—Subject to Change Without Notice
SI2
Symbol
C
S
S
host
rise
fall
SI1
Min
—
—
—
Table 20
Max
1.25
1.25
20
Freescale Semiconductor
lists the timing
Unit
V/ns
V/ns
pF