HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 4

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
4.4
4.5
5
6
6.1
6.2
6.3
6.4
7
7.1
7.2
7.3
8
8.1
8.2
9
9.1
9.2
10
10.1
10.2
11
12
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6.4.1
6.4.2
Electrical characteristics ................................................................................................................. 48
Timing characteristics ..................................................................................................................... 51
S/T interface circuitry...................................................................................................................... 56
State matrices for NT and TE ......................................................................................................... 61
Binary organisation of the frames .................................................................................................. 63
Clock synchronisation...................................................................................................................... 65
HFC-S+ package dimensions .......................................................................................................... 67
ISDN PC card sample circuitry with HFC-S+ .............................................................................. 68
Register bit description of CONNECT register............................................................................. 42
Register bit description of interrupt, status and control registers.................................................. 43
ISA-PC bus or processor access .................................................................................................... 51
SRAM access ................................................................................................................................. 52
GCI/IOM2 bus clock and data alignment for Mitel ST
GCI/IOM2 timing .......................................................................................................................... 54
External receiver circuitry ............................................................................................................. 56
External transmitter circuitry......................................................................................................... 57
Oscillator circuitry ......................................................................................................................... 60
S/T interface activation/deactivation layer 1 for finite state matrix for NT .................................. 61
Activation/deactivation layer 1 for finite state matrix for TE ....................................................... 62
S/T frame structure ........................................................................................................................ 63
GCI frame structure ....................................................................................................................... 64
Clock synchronisation in NT-mode........................................................................................... 65
Clock synchronisation in TE-mode ........................................................................................... 66
Master mode.......................................................................................................................... 54
Slave mode ............................................................................................................................ 55
TM
bus....................................................... 53
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Cologne
Chip