HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 2

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
Revision History
Cologne Chip AG
Eintrachtstrasse 113
D-50668 Köln
Germany
Tel.: +49 (0) 221 / 912 96 04
Fax: +49 (0) 221 / 912 96 05
http://www.CologneChip.com
http://www.CologneChip.de
[e-mail]
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Date
Jan. 2001
Feb. 2000
Nov. 1999
Aug. 1999
Mar. 1999
Feb. 1999
Aug. 1998
May 1998
Cologne
Chip
Remarks
Information added to section: Power down considerations.
Information added to section: Processor interface modes, processor mode, FIFO
channel operation: receive channels, STATES register bit description, ISA-PC bus
or processor access timing, S/T interface activation/deactivation layer 1 for finite
state matrix for NT.
Changes made on: S/T modules part numbers and manufacturers.
Changes made on: DMA access in processor mode, Register bit description of
GCI/IOM2 bus section: Auxiliary channel handling, B_MODE register bit
description.
Changes made on: RESET characteristics, FIFO change must no longer be made
twice, watchdog/timer, automatically D-channel frame repetition, transparent mode,
power down considerations, TRxR register bit description, TRM register bit
description, SRAM access, S/T module part numbers and manufacturers, sample
circuitry.
Information added to section: GCI/IOM2 timing.
Information added to section: DMA access in processor mode, GCI frame structure.
Section added: Configuring test loops.
Changes made on: CLKDEL register bit description.
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Cologne
Chip