HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 33

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
3.8
For the FIFO data an 32K x 8 external SRAM is used. A 8K x 8 external SRAM is also possible but not
recommended.
The required access time is 80 ns or below.
1024 Bytes of the external SRAM are reserved for internal HFC-SP use.
Table 4: SRAM and FIFO size
To initialise the HFC-S for 8K x 8 SRAM use:
For all further accesses to the CIRM register bit 4 must be set.
3.9
For very low power consumption the oscillator of the HFC-S+ can be stopped. Furthermore the external
SRAM is disabled (/SR_CS=1). To avoid current generated by floating inputs the data bus of the SRAM
and all other inputs must be put to GND or VDD. So it is useful to connect the SRAM data bus to a
resistor array of about 1M . If the HFC-S+ is operated in processor mode the unused interrupt lines (and
watchdog lines) should not be left open. They should be connected to VDD or GND over a resistor to
reduce current.
If the oscillator is stopped and the awake option is disabled the supply current is reduced to less than
1mA.
:Q^eQbi " !
*
If you connect the HFC-S+ with the SRAM you can simplify PCB layout if you permutate address
lines and data lines. If you connect data lines of the SRAM with data lines of the HFC-S+ and SR-
address lines of the HFC-S+ with address lines of the SRAM you can do this in any order.
hint!
External SRAM
External SRAM
- write 18h to the CIRM register
- wait at least 4 clock cycles
- write 10h to the CIRM register
Power down considerations
32K x 8
8K x 8
per channel and direction
B-channel FIFO size
1536 Bytes
7680 Byte
D-channel FIFO size
per direction
512 Bytes
512 Byte
Cologne
Chip
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