HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 3

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Contents
1
1.1
1.2
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
4
4.1
4.2
4.3
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1.2.1
1.2.2
3.3.1
3.4.1
3.4.2
3.4.3
3.4.4
3.7.1
3.7.2
General description............................................................................................................................ 6
Pin description.................................................................................................................................... 9
Functional description ..................................................................................................................... 16
3.4.1.1
3.4.1.2
3.7.1.1
3.7.1.2
3.7.1.3
3.7.1.4
3.7.1.5
3.7.1.6
Register bit description.................................................................................................................... 35
Applications ..................................................................................................................................... 7
Mode description ............................................................................................................................. 8
ISA-PC bus and microprocessor interface....................................................................................... 9
S/T interface transmit signals ........................................................................................................ 11
S/T interface receive signals.......................................................................................................... 11
SRAM Interface ............................................................................................................................. 12
Oscillator........................................................................................................................................ 12
GCI/IOM2 bus interface ................................................................................................................ 13
GCI/IOM2 Timeslot enable signals ............................................................................................... 13
Interrupt outputs............................................................................................................................. 14
Miscellaneous pins......................................................................................................................... 14
ISA-PC mode ................................................................................................................................. 16
ISA-PC bus interface ..................................................................................................................... 18
Processor mode .............................................................................................................................. 19
Internal HFC-S+ register description............................................................................................. 21
Timer.............................................................................................................................................. 26
Watchdog ....................................................................................................................................... 26
FIFOs ............................................................................................................................................. 27
External SRAM.............................................................................................................................. 33
Power down considerations ........................................................................................................... 33
Register bit description of the FIFO select register ....................................................................... 35
Register bit description of S/T section .......................................................................................... 35
Register bit description of GCI/IOM2 bus section ........................................................................ 39
Power supply ............................................................................................................................. 15
RESET characteristics............................................................................................................... 15
Configuring test loops ............................................................................................................... 34
ISA-PC mode .......................................................................................................................... 8
Processor interface modes....................................................................................................... 8
DMA access in processor mode............................................................................................ 20
FIFO control registers ........................................................................................................... 21
Registers of the S/T section .................................................................................................. 23
Registers of the GCI/IOM2 bus section ................................................................................ 24
Interrupt and status registers ................................................................................................. 25
FIFO channel operation......................................................................................................... 28
Transparent mode of HFC-S+ ............................................................................................... 32
FIFO select register........................................................................................................... 21
FIFO registers ................................................................................................................... 21
Send channels (B1, B2 and D transmit)............................................................................ 29
Automatically D-channel frame repetition ....................................................................... 29
FIFO full condition in send channels................................................................................ 29
Receive Channels (B1, B2 and D receive) ....................................................................... 30
FIFO full condition in receive channels ........................................................................... 31
FIFO reset ......................................................................................................................... 32
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