HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 10

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
1)
! _V '
Pin No.
open drain, external pull up resistor required
13
14
15
16
17
18
21
22
23
24
25
26
27
28
31
32
*
If DMA acknowledge signals /DMAAK0 and /DMAAK1 are active, the function of the
read/write enables is inverted. This means a read command on the controller databus
writes the AUX-Channel register and a write command reads the register. The address on
the address bus (SA0-SA7) is ignored.
important!
SA8
/DMAAK0
SA9
/AEN
/CS
IOCHRDY
/WAIT
/IOR
/DS
/IOW
R/W
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BUSDIR
ALE
/DMAAK1
Pin Name
Output
Input
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
1)
1)
1
2,3,4
1
2,3,4
1,3,4
2
1,3,4
2
all
all
all
all
all
all
all
all
1,2,3,4
1
2,3,4
1
2,3,4
Mode
PC bus address enable
chipselect low active
I/O channel ready
low active wait signal for external processor
I/O read enable
I/O data strobe
I/O write enable
Read/Write select (WR='0')
Databus bit 0 (LSB)
Databus bit 1
Databus bit 2
Databus bit 3
Databus bit 4
Databus bit 5
Databus bit 6
Databus bit 7 (MSB)
'0'
Address latch enable
ALE is also used for mode selection of the HFC-S+.
See Mode selection on page 8 for detailed
information.
Databus direction signal for external busdriver
Function
Address bit 8
DMA acknowledge channel 0
Direct access to GCI/IOM2 bus AUX1 channel data
register (low active)
address bit 9
DMA acknowledge channel 1
direct access on GCI/IOM2 bus AUX2 channel
dataregister (low active)
BD0-BD7 are outputs
:Q^eQbi " !
Cologne
Chip