HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 14

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
2.8
1)
2)
2.9
!$ _V '
Pin No.
100
94
95
96
97
98
99
49
open drain, external pull up resistor required
open source, external pull down resistor required
Interrupt outputs
Miscellaneous pins
IRQ_A
/IRQ_P
IRQ_B
IRQ_P
IRQ_C
/WD_RES
IRQ_D
WD_RES
IRQ_E
DMARQ0
IRQ_F
DMARQ1
NC
RESET
Pin Name
Output
Input
O
O
O
O
I/O
O
O
O
O
O
O
O
I
1)
2)
1)
2)
1
2,3,4
1
2,3,4
1
2,3,4
1
2,3,4
1
2,3,4
1
2,3,4
all
Mode
Function
PC bus interrupt request A or interrupt input from
external device (see: CIRM register bit description)
processor interrupt request low active
PC bus interrupt request B
processor interrupt request high active
PC bus interrupt request C
Watchdog expired, external reset low active
PC bus interrupt request D
Watchdog expired, external reset high active
PC bus interrupt request E
DMA request AUX1 channel register (high active)
PC bus interrupt request F
DMA request AUX2 channel register (high active)
Not connected (leave pin open)
Reset for HFC-S+ (high active)
:Q^eQbi " !
Cologne
Chip