HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 15

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
2.10
2.11
The reset signal (hardware reset or software reset) must be active for at least 4 clock cycles.
The GCI/IOM2 bus lines STIO1, STIO2 and the interrupt lines are in tristate mode after a reset.
The HFC-S+ is in slave mode after reset. C4IO and F0IO are inputs.
In the processor modes DMARQ1 and DMARQ2 are inactive ('0').
The S/T state machine is stuck to '0' after reset. This means the HFC-S+ does not react to any signal on
the S/T interface before the S/T state machine is initialised.
The registers' initial values are described in the Register bit description (section 4 of this data sheet).
After RESET the HFC-S+ is in an initialisation cycle and is therefor busy for a maximum of 160 clock
cycles.
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19, 30, 41, 42, 51, 61, 84, 89
20, 29, 33, 39, 40, 47, 52, 62,
73, 81, 90, 93
*
All power supply pins VDD must be directly connected to each other. Also all pins GND must be
directly connected to each other.
To keep VDD and GND bounce to a minimum a bypass capacitor (10 nF to 100 nF) should be
placed between each pair of VDD/GND pins.
important!
Power supply
RESET characteristics
Pin No.
VDD
GND
Pin Name
Function
VDD (+3V to +5V)
GND
Cologne
Chip
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